Ansys EMC+ – Thin Wire Circuits

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Introduction

Ansys EMC+ is a platform-level EMC modeling and simulation software, capable of modeling phenomena such as radiated emissions, shielding effectiveness, and cable signal integrity. This article is going to focus on defining thin wire structures in Ansys EMC+, which can be used to create arbitrary RLC circuit elements alongside Current and Voltage sources to drive your 3D electromagnetic projects. We will be creating a simple circuit to charge a capacitor using a current source, and then close a switch to discharge the collected capacitor energy through a resistor.

Thin Wire Elements in Ansys EMC+

Thin wires are directional conductors that have a cylindrical shape, a defined beginning and end, and a diameter. They are made from simple line geometry that is drawn within Ansys Discovery, which is the tool that the Ansys EMC+ solver lives inside of in the Ansys Electronics ecosystem. They can be assigned a resistance and/or inductance per-meter, which combined with the line’s length determines the R and/or L characteristics of the structure. Each end of a thin wire can also be terminated with a resistor, inductor, or capacitor. The figure below shows what this looks like as a series of lumped elements.

A partial circuit schematic of the termination of a thin wire structure in EMC+

Zm is the impedance of the material that the thin wire terminates into and is automatically calculated by the solver depending on the material’s electrical properties. The ground represents the bond to the material, rather than a true circuit ground in the traditional sense. The termination RLC components are in series with the wire’s inherent RLC properties.

Simple Discharge Circuit

This tutorial is going to create the following discharge circuit inside of Ansys EMC+:

A circuit schematic from the SPICE simulation used to compare to the 3D simulation

The current source I1 is a pulsed current source that will be used to charge the 10 nF capacitor, C1. The pulse has a rise and fall time of 1 ns, a total pulse width of 10 ns, and a current amplitude of 1 kA. The switch S1 has an off-resistance of 100 kΩ and an on-resistance of 1 nΩ, to closely simulate a PEC when discharging. The switch triggers 100 ns into the simulation. The resistor R2 has a large magnitude to simulate the circuit floating, since our discharge circuit in EMC+ will not have a ground. The current waveform through the 5 Ω load resistor can be seen in the next figure.

A waveform of the current through the load resistor of the circuit schematic from the simple SPICE model

Discharge Circuit in Ansys EMC+

Thin wires in Ansys EMC+ are defined on line geometry drawn in a 2D plane. They can be drawn in any of the regular cartesian planes of XY, XZ, or YZ, and should be aligned to the global grid at values that align with the space step size of your simulation domain. For this example, our space steps in X, Y, and Z are all 5 mm, so each line is drawn at a position and with a length that are each divisible by 5 mm. The current source (I Source), capacitor (C1), and switch lines are all 20 mm in length, and the resistor lines, Rs1, Rs2, and R1, are all 10 mm in length.

Representation of thin wire circuit in Ansys EMC+

Each thin wire component has a defined radius of 0.5 mm, and the lumped values assigned to them match those of the spice circuit from before. It is important to note that when creating this geometry and including elements that have directionality to them (like a current source), the direction of the line geometry when it was initially drawn will be the direction of current flow. For this example, the line for the current source was drawn from the negative X to the positive X direction, thus making the current initially flow in the positive X direction.

Ansys EMC+ Waveforms

Once our circuit is set up, we can run our Ansys EMC+ simulation and get the current flowing through our load resistor, R1, when the switch is closed. The first 10 ns of the simulation are for the capacitor to charge to approximately 1 kV, and then the switch is closed 100 ns into the simulation, the same as in our simple Spice model. The current through R1 can be seen below:

A waveform of the current through the load resistor of the circuit schematic using the EMC+ model

We can immediately see that there are some differences here – the peak current is a little bit lower, the rise time is slower, and the overall pulse width is shorter.

So, why is this so different from our initial circuit model? If you recall, when we were defining our thin wire components in EMC+ it asked us for a wire radius, for which we used the value of 0.5 mm. The thin wire solver then uses this value, in conjunction with the rest of the wires and the loop that they form, to calculate the parasitic inductances inherent to the circuit, which our initial spice model did not consider – but we can change that.

New SPICE Discharge Circuit

We can estimate the self-inductance of our wires using the following equation:

The equation used to calculate the self-inductance of a thin wire

Where Lwire is the inductance we will calculate (in nH), l is the wire length in cm, and d is the wire diameter in cm. The final variable, µr, is the relative permeability of the conductor, which for most cases (including this one) will be 1. Plugging in our values from before, we get the following parasitic series inductances for all our components:

ComponentParasitic Series Inductance (nH)
Isource14.6
Rs1,25.98
C114.6
R15.98

There is also a loop inductance value based on the physical representation of the circuit in EMC+ that will impact our result; this was estimated to be around 67 nH. Our new spice circuit looks like this:

A circuit schematic from the SPICE simulation updated with the parasitic inductance values previously calculated.

And if we plot the current through our load resistor on top of the results from our Ansys EMC+ simulation we get a good correlation between the two solvers:

A pair of overlaid waveforms, one from each of the SPICE model and the EMC+ model, showing that the updated SPICE model accurately predicts the EMC+ model

Conclusion

With this, we have demonstrated how to create a circuit of simple elements in Ansys EMC+ and a method of usefully comparing that circuit to a simpler SPICE model. By understanding how the solver works and where the parasitic values come from, we can use these circuit elements to drive more complex 3D problem spaces to explore phenomena such as electric breakdown, electrostatic discharge, and EMI/EMC problems related to these. Understanding circuit elements in EMC+ is critical to ensuring that the inputs to these more complicated problems are understood and predictable, which allows for more robust and realistic 3D simulations. If you would like to learn more about Ansys EMC+ or other simulation tools and services we offer here at PADT, you can do so on our website here.

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