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There are three main goals of the licensing changes in the latest release of ANSYS:
Why is this significant? Well, this was always a sticking point for our customers when upgrading from one version to the next.
Here’s how that usually plays out:
Download the latest license manager through the Ansys customer portal:
Follow installation instructions and add the latest license file:
Make sure license server is running and has the correct licenses queued:
This was a high-level flyover of the new Ansys Licensing released with version 2020R1. For specifics contact your PADT Account manager or support@padtinc.com .
In this article I will cover a Voltage Drop (DC IR) simulation in SIwave, applying realistic power delivery setup on a simple 4-layer PCB design. The main goal for this project is to understand what data we receive by running DC IR simulation, how to verify it, and what is the best way of using it.
And before I open my tools and start diving deep into this topic, I would like to thank Zachary Donathan for asking the right questions and having deep meaningful technical discussions with me on some related subjects. He may not have known, but he was helping me to shape up this article in my head!
There are many different power nets present on the board under test, however I will be focusing on two widely spread nets +1.2V and +3.3V. Both nets are being supplied through Voltage Regulator Module (VRM), which will be assigned as a Voltage Source in our analysis. After careful assessment of the board design, I identified the most critical components for the power delivery to include in the analysis as Current Sources (also known as ‘sinks’). Two DRAM small outline integrated circuit (SOIC) components D1 and D2 are supplied with +1.2V. While power net +3.3V provides voltage to two quad flat package (QFP) microcontrollers U20 and U21, mini PCIE connector, and hex Schmitt-Trigger inverter U1.
Figure 1 shows the ‘floor plan’ of the DC IR analysis setup with 1.2V voltage path highlighted in yellow and 3.3V path highlighted in light blue.
Before we assign any Voltage and Current sources, we need to define pin groups for all nets +1.2V, +3.3V and GND for all PDN component mentioned above. Having pin groups will significantly simplify the reviewing process of the results. Also, it is generally a good practice to start the DC IR analysis from the ‘big picture’ to understand if certain component gets enough power from the VRM. If a given IC reports an acceptable level of voltage being delivered with a good margin, then we don’t need to dig deeper; we can instead focus on those which may not have good enough margins.
Once we have created all necessary pin groups, we can assign voltage and current sources. There are several ways of doing that (using wizard or manual), for this project we will use ‘Generate Circuit Element on Components’ feature to manually define all sources. Knowing all the components and having pin groups already created makes the assignment very straight-forward. All current sources draw different amount of current, as indicated in our setting, however all current sources have the same Parasitic Resistance (very large value) and all voltage source also have the same Parasitic Resistance (very small value). This is shown on Figure 2 and Figure 3.
Note: The type of the current source ‘Constant Voltage’ or ‘Distributed Current’ matters only if you are assigning a current source to a component with multiple pins on the same net, and since in this project we are working with pins groups, this setting doesn’t make difference in final results.
For each power net we have created a voltage source on VRM and multiple current sources on ICs and the connector. All sources have a negative node on a GND net, so we have a good common return path. And in addition, we have assigned a negative node of both voltage sources (one for +1.2V and one for +3.3V) as our reference points for our analysis. So reported voltage values will be referenced to that that node as absolute 0V.
At this point, the DC IR setup is complete and ready for simulation.
When the DC IR simulation is finished, there is large amount of data being generated, therefore there are different ways of viewing results, all options are presented on Figure 4. In this article I will be primarily focusing on ‘Power Tree’ and ‘Element Data’. As an additional source if validation we may review the currents and voltages overlaying the design to help us to visualize the current flow and power distribution. Most of the time this helps to understand if our assumption of pin grouping is accurate.
First let’s look at the Power Tree, presented on Figure 5. Two different power nets were simulated, +1.2V and +3.3V, each of which has specified Current Sources where the power gets delivered. Therefore, when we analyze DC IR results in the Power tree format, we see two ‘trees’, one for each power net. Since we don’t have any pins, which would get both 1.2V and 3.3V at the same time (not very physical example), we don’t have ‘common branches’ on these two ‘trees’.
Now, let’s dissect all the information present in this power tree (taking in consideration only one ‘branch’ for simplicity, although the logic is applicable for all ‘branches’):
This option shows us results in the tabular representation. It lists many important calculated data points for specific objects, such as bondwire, current sources, all vias associated with the power distribution network, voltage probes, voltage sources.
Let’s continue reviewing the same power net +1.2V and the power distribution to CPU1 component as we have done for Power Tree (Figure 5). The same way we will be going over the details in point-by-point approach:
To verify the reported voltage values, we can place Voltage Probes (under circuit elements). Once we do that, we will need to rerun the simulation in order to get the results for the probes:
If we have 1.2V at the positive pin of VRM, then voltage drops 222.464mV across the power plane, so the positive pin of IC gets supplied with 0.977V. Then the voltage at the Current Source 0.724827V (8) being drawn, leaving us with (1.2V – 0.222464V – 0.724827V) = 0.252709V at the negative pin of the Current Source. On the return path the voltage drops again across the ground plane 252.4749mV (14) delivering back at the negative pin of VRM (0.252709V – 0.252475V) = 234uV. This is the internal voltage drop in the Voltage Source, as calculated as output current at VRM 234A (7) multiplied by Parasitic Resistance 1E-6Ohm (Figure 3) at VRM. This is Series R Voltage (11)
In addition to all provided above calculations and explanations, the video below in Figure 7 highlights all the key points of this article.
By carefully reviewing the Power Tree and Element Data reporting options, we can determine many important decisions about the power delivery network quality, such as how much voltage gets delivered to the Current Source; how much voltage drop is on the power net and on the ground net, etc. More valuable information can be extracted from other DC IR results options, such as ‘Loop Resistance’, ‘Path Resistance’, ‘RL table’, ‘Spice Netlist’, full ‘Report’. However, all these features deserve a separate topic.
As always, if you would like to receive more information related to this topic or have any questions please reach out to us at info@padtinc.com.
HFSS offers different method of creating and simulating a large array. The explicit method, shown in Figure 1(a) might be the first method that comes to our mind. This is where you create the exact CAD of the array and solve it. While this is the most accurate method of simulating an array, it is computationally extensive. This method may be non-feasible for the initial design of a large array. The use of unit cell (Figure 1(b)) and array theory helps us to start with an estimate of the array performance by a few assumptions. Finite Array Domain Decomposition (or FADDM) takes advantage of unit cell simplicity and creates a full model using the meshing information generated in a unit cell. In this blog we will review the creation of unit cell. In the next blog we will explain how a unit cell can be used to simulate a large array and FADDM.
In a unit cell, the following assumptions are made:
A unit cell works based on Master/Slave (or Primary/Secondary) boundary around the cell. Master/Slave boundaries are always paired. In a rectangular cell you may use the new Lattice Pair boundary that is introduced in Ansys HFSS 2020R1. These boundaries are means of simulating an infinite array and estimating the performance of a relatively large arrays. The use of unit cell reduces the required RAM and solve time.
Primary/Secondary (Master/Slave) (or P/S) boundaries can be combined with Floquet port, radiation or PML boundary to be used in an infinite array or large array setting, as shown in Figure 3.
To create a unit cell with P/S boundary, first start with a single element with the exact dimensions of the cell. The next step is creating a vacuum or airbox around the cell. For this step, set the padding in the location of P/S boundary to zero. For example, Figure 4 shows a microstrip patch antenna that we intend to create a 2D array based on this model. The array is placed on the XY plane. An air box is created around the unit cell with zero padding in X and Y directions.
You notice that in this example the vacuum box is larger than usual size of quarter wavelength that is usually used in creating a vacuum region around the antenna. We will get to calculation of this size in a bit, for now let’s just assign a value or parameter to it, as it will be determined later. The next step is to define P/S to generate the lattice. In AEDT 2020R1 this boundary is under “Coupled” boundary. There are two methods to create P/S: (1) Lattice Pair, (2) Primary/Secondary boundary.
Lattice Pair
The Lattice Pair works best for square lattices. It automatically assigns the primary and secondary boundaries. To assign a lattice pair boundary select the two sides that are supposed to create infinite periodic cells, right-click->Assign Boundary->Coupled->Lattice Pair, choose a name and enter the scan angles. Note that scan angles can be assigned as parameters. This feature that is introduced in 2020R1 does not require the user to define the UV directions, they are automatically assigned.
Primary/Secondary boundary is the same as what used to be called Master/Slave boundary. In this case, each Secondary (Slave) boundary should be assigned following a Primary (Master) boundary UV directions. First choose the side of the cell that Primary boundary. Right-click->Assign Boundary->Coupled->Primary. In Primary Boundary window define U vector. Next select the secondary wall, right-click->Assign Boundary->Couple->Secondary, choose the Primary Boundary and define U vector exactly in the same direction as the Primary, add the scan angles (the same as Primary scan angles)
Floquet port excites and terminates waves propagating down the unit cell. They are similar to waveguide modes. Floquet port is always linked to P/S boundaries. Set of TE and TM modes travel inside the cell. However, keep in mind that the number of modes that are absorbed by the Floquet port are determined by the user. All the other modes are short-circuited back into the model. To assign a Floquet port two major steps should be taken:
Defining Floquet Port
Select the face of the cell that you like to assign the Floquet port. This is determined by the location of P/S boundary. The lattice vectors A and B directions are defined by the direction of lattice (Figure 7).
The number of modes to be included are defined with the help of Modes Calculator. In the Mode Setup tab of the Floquet Port window, choose a high number of modes (e.g. 20) and click on Modes Calculator. The Mode Table Calculator will request your input of Frequency and Scan Angles. After selecting those, a table of modes and their attenuation using dB/length units are created. This is your guide in selecting the height of the unit cell and vaccume box. The attenation multiplied by the height of the unit cell (in the project units, defined in Modeler->Units) should be large enough to make sure the modes are attenuated enough so removing them from the calcuatlion does not cause errors. If the unit cell is too short, then you will see many modes are not attenuated enough. The product of the attenuatin and height of the airbox should be at least 50 dB. After the correct size for the airbox is calcualted and entered, the model with high attenuation can be removed from the Floquet port definition.
The 3D Refinement tab is used to control the inclusion of the modes in the 3D refinement of the mesh. It is recommended not to select them for the antenna arrays.
In our example, Figure 8 shows that the 5th mode has an attenuation of 2.59dB/length. The height of the airbox is around 19.5mm, providing 19.5mm*2.59dB/mm=50.505dB attenuation for the 5th mode. Therefore, only the first 4 modes are kept for the calculations. If the height of the airbox was less than 19.5mm, we would need to increase the height so accordingly for an attenuation of at least 50dB.
Radiation Boundary
A simpler alternative for Floquet port is radiation boundary. It is important to note that the size of the airbox should still be kept around the same size that was calculated for the Floquet port, therefore, higher order modes sufficiently attenuated. In this case the traditional quarter wavelength padding might not be adequate.
Perfectly Matched Layer
Although using radiation boundary is much simpler than Floquet port, it is not accurate for large scan angles. It can be a good alternative to Floquet port only if the beam scanning is limited to small angles. Another alternative to Floquet port is to cover the cell by a layer of PML. This is a good compromise and provides very similar results to Floquet port models. However, the P/S boundary need to surround the PML layer as well, which means a few additional steps are required. Here is how you can do it:
*Please note for this method, an auto-size “region” cannot be used, instead draw a box for air/vacuum box. The region does not let you create the faces you need to combine with PML faces.
The advantage of PML termination over Floquet port is that it is simpler and sometimes faster calculation. The advantage over Radiation Boundary termination is that it provides accurate results for large scan angles. For better accuracy the mesh for the PML region can be defined as length based.
Seed the Mesh
To improve the accuracy of the PML model further, an option is to use length-based mesh. To do this select the PML box, from the project tree in Project Manager window right-click on Mesh->Assign Mesh Operation->On Selection->Length Based. Select a length smaller than lambda/10.
Scanning the Angle
In phased array simulation, we are mostly interested in the performance of the unit cell and array at different scan angles. To add the scanning option, the phase of P/S boundary should be defined by project or design parameters. The parameters can be used to run a parametric sweep, like the one shown in Figure 12. In this example the theta angle is scanned from 0 to 60 degrees.
Comparing PML and Floquet Port with Radiation Boundary
To see the accuracy of the radiation boundary vs. PML and Floquet Port, I ran the simulations for scan angles up to 60 degrees for a single element patch antenna. Figure 13 shows that the accuracy of the Radiation boundary drops after around 15 degrees scanning. However, PML and Floquet port show similar performance.
S Parameters
To compare the accuracy, we can also check the S parameters. Figure 14 shows the comparison of active S at port 1 for PML and Floquet port models. Active S parameters were used since the unit cell antenna has two ports. Figure 15 shows how S parameters compare for the model with the radiation boundary and the one with the Floquet port.
The unit cell definition and options on terminating the cell were discussed here. Stay tuned. In the next blog we discuss how the unit cell is utilized in modeling antenna arrays.