All Things Ansys 063: Fighting COVID-19 with Ansys Simulation


Published on: May 18th, 2020
With: Eric Miller, Thierry Marchal & Marc Horner

In this episode your host and Co-Founder of PADT, Eric Miller is joined by two leaders in the Ansys response to COVID-19 – Thierry Marchal, Global Industry Director for Healthcare, Consumer Products & Construction, and Marc Horner, Principal Healthcare Engineer – for a discussion on what the company is doing to combat the spread of the virus, as well as give our listeners a more complete understanding regarding the specific applications that Ansys tools are being used for during this global pandemic.

If you would like to learn more about Ansys and their response to COVID-19, check out the following link:

If you have any questions, comments, or would like to suggest a topic for the next episode, shoot us an email at we would love to hear from you!



Panel Discussion: Fighting COVID-19 with 3D Printing

When the virus that causes COVID-19 started to spread around the world, supply chains started to fail. The made access to personal protective equipment, or PPE, even more difficult. That is when Additive Manufacturing stepped up and said: “We can help.”Check now touroftoowoomba for upcoming updates.

PADT held a panel discussion with three customers and our partner, Stratasys, to hear how each of them met the challenges posed by COVID-19 and responded with 3D Printing. It was a fantastic discussion and well worth a listen.

Designing Better Rocket Engines with Ansys – Webinar

In 2017 Colorado based company Ursa Major Technologies put together an expert team of designers and engineers to realize its vision of providing the microsatellite industry with the best rocket engines in the business. Utilizing Ansys simulation software, additive manufacturing, and modernizing staged combustion, the company successfully designed and built two liquid oxygen and kerosene engines and has a third engine in development.

With Ansys, Ursa Major Technologies is accomplishing design goals faster and more efficiently than ever before. Using Finite Element Analysis (FEA), the company can run models with 30-40 unique parts to analyze entire turbo pumps in one simulation. Thrust analysis, which the company had previously done with 2D models, can now be done all in the Ansys CFX tool more cost-effectively.

Join PADT and Ursa Major Technologies for a brief overview of applications for Ansys in the aerospace industry, followed by an exploration of how they are using these simulation tools to better design and optimize the next generation of rocket engines.

Register Here

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Changes to Licencing at ANSYS 2020R1

There are three main goals of the licensing changes in the latest release of ANSYS:

  • Deliver Ansys licensing using the FlexLM industry standard
  • Eliminate the Ansys licensing interconnect
  • Provide modular licensing options that are easier to understand
  • Finally – and this is the whopper (or Double Double if you’re an In-N-Out kind of analogy person) – this new licensing model eliminates the need for upgrading the Ansys License Manager with every software update. (please pause for shock recovery)
If you’re still shocked and would to like see a “shocked groundhog” compilation, check this out.

Why is this significant? Well, this was always a sticking point for our customers when upgrading from one version to the next.

Here’s how that usually plays out:

  1. Engineers eager to try out new features or overcome software defects, download the software and install it on their workstations.
    1. Surprise – software throws an obscure licensing error.
    2. Engineer notifies IT or Ansys Channel partner of issue.
    3. After a few calls, maybe a screenshare or two, its determined that the license server needs to be upgraded.
    4. The best-case scenario – IT or PADT Support can get it installed in a few minutes and engineer can be on his way.
    5. The usual scenario – it will take a week to schedule downtime on the server and notify all stakeholders and the engineer is left to simmer on medium-low until those important safeguards are handled.

What does this all mean?

  • Starting in January 2020, all new Ansys keys issued will be in the new format and will require upgrading to the 2020R1 License manager. This should be the last mandatory license server upgrade for a while.
  • Your Ansys Channel Partner will contact you ahead of your next renewal to discuss new license increments and if there are any expected changes.
  • Your IT and Ansys support team will be celebrating in the back office the last mandatory Ansys License Manager upgrade for a while.

How to upgrade the Ansys License Manager?

Download the latest license manager through the Ansys customer portal:

Follow installation instructions and add the latest license file:

  • Ansys has a handy video on this here
  • Make sure that you run the installed as an administrator for best results.

Make sure license server is running and has the correct licenses queued:

  • Look for the green checkmark in the license management center window.
  • Start your application and make sure everything looks good.

This was a high-level flyover of the new Ansys Licensing released with version 2020R1. For specifics contact your PADT Account manager or .

Introducing the Stratasys J55 3D Printer – Possibilities at Every Turn

From perfecting products to applying concepts learned in the classroom, Stratasys can help you realize any number of design ideas. The new J55 introduces a rotating print platform for outstanding surface finish and printing quality, and features multimaterial capabilities and material configurations for both industrial and mechanical design.

The Stratasys J55 3D Printer is a huge leap forward for accessible, full color 3D printing and allows designers to have multiple iterations of a prototype ready and at their fingertips throughout every phase of the design process.

Enhanced 3D printing capabilities include – static print head, rotating build tray, UV LED illumination technology, new material cartridge design, and more. The full reliability and quality of PolyJet technology created for an office or studio environment, at an affordable price.

Designed for consistent, stable performance, the J55 requires zero mechanical calibrations and features a “ready-to-print” mode, so you can make ideas a reality without interruption.

Click the link below to download the product brochure and learn how this innovative new machine is revolutionizing the world of additive manufacturing. 

All Things Ansys 062: Optimizing Materials Selection for Additive Manufacturing with Ansys Granta


Published on: May 4th, 2020
With: Eric Miller, Pam Waterman & Robert McCathren

In this episode your host and Co-Founder of PADT, Eric Miller is joined by PADT’s Pam Waterman and Robert McCathren for a discussion on how Ansys Granta can be used to help optimize hardware selection for additive manufacturing. The Senvol Database details 1,000 AM machines and more than 850 compatible materials. Using this tool within Granta Selector, you can search and compare materials based on properties, type, or compatible machines.

If you would like to learn more about the Ansys tool and it’s applications for additive, check out our webinar on the topic here:

If you have any questions, comments, or would like to suggest a topic for the next episode, shoot us an email at we would love to hear from you!



Example of full color part with mapped image, created from 3MF file format brought into GrabCAD Print and printed on a Stratasys PolyJet 3D printer. (Image courtesy GrabCAD)

3MF Printing Format Comes to GrabCAD Print

Example of full color part with mapped image, created from 3MF file format brought into GrabCAD Print and printed on a Stratasys PolyJet 3D printer. (Image courtesy GrabCAD)

Example of full color part with mapped image, created from a 3MF file-format brought into GrabCAD Print and set up to print on a Stratasys PolyJet 3D printer. (Image courtesy GrabCAD)

What is the 3MF format? How does it differ from the standard STL format? And what can you do with it, especially if your 3D printers run GrabCAD Print software from Stratasys?

For most designers, engineers and users involved in 3D printing, regardless of the 3D CAD software you use, you save (convert) your model to print as an STL format file. A lot has been written about it, including a PADT post from back in 2012 – and STL-wise, things really haven’t changed. This format approximates the native CAD solid model as a closed surface comprising small triangles of various shapes and sizes. STL has been the standard since the AM industry began, and although different CAD packages use different algorithms to create the mesh, for the most part, it’s worked pretty well.

A Sample STL File Segment

However, an STL file is simply a large text file listing the Cartesian coordinates for each vertex of the thousands of triangles, along with info on the normal direction:

Sample code from saving a CAD model in STL format.

A modest number of large triangles produces relatively small files but doesn’t do a good job of reproducing curves (think highly faceted surfaces); conversely, big files of many small triangles produce much smoother transitions but can take a long time to process in slicing software.

And, perhaps the biggest negative is that an STL file cannot include any other information: desired color, desired material, transparency, internal density gradient, internal fine structure or more.

What is 3MF?

In early 2015, Microsoft and a number of other major corporations including Autodesk, Dassault Systèmes, HP, Shapeways and SLM Group created a consortium to address these issues. They decided to overhaul a little-used file format called the 3D Modeling Format (3MF), to make it support highly detailed 3D model information and be more useful for 3D printing and related processes.

Logo 3MF Consortium

This ongoing consortium project defines 3MF as “a set of conventions for using XML to describe the appearance and structure of 3D models for the purpose of manufacturing (3D printing).”

In developer language, 3MF is a standard package or data that follows a core specification and may include some task-specific extensions.

In user terms, a 3MF file contains some or all of the following information in ASCII format:

  • Metadata about part name, creator and date
  • Information on the mesh of triangles (yes, it still creates and uses these, but does it better for a number of reasons, one of which is that it cannot create non-manifold edges (i.e., triangles that share endpoints with more than one triangle, which confuses the printer))
  • Color information (throughout the complete part body or in sub-sections)
  • Ways to define multiple materials combined as a composite
  • Texture information – what it is and where to place it
  • Ways to assign different materials to different sections of a part
  • Ways to duplicate information from one section of a part to another section, to save memory
  • Slicing instructions

Without getting into the nitty gritty, here are just two examples of XML code lines from 3MF metadata sections:

Example code of saving a solid CAD model in 3MF format.

Meaning, information about the part number and the part color rides along with the vertex coordinates! For a deep-dive into the coding schema, including a helpful glossary, see the 3MF github site; to learn how 3MF compares to STL, OBJ, AMF, STEP and other formats, check out the consortium’s About Us page.

Exporting 3MF Files

Now, how about using all of this? Where to start? Many 3D CAD software packages now let you save solid models as 3MF files (check out your “Save As” drop-down menu to verify), but again, they can vary as to what information is being saved. For example, a SolidWorks 3MF file can generate data on color and material but does not yet support transparency.

Here are all the options that you see in SolidWorks when you click the arrow next to “Save As”:

Second step in SolidWorks for saving a file in 3MF format: check off “include materials” and “include appearance.” (Image courtesy PADT)

“Save As” window in SolidWorks 2019, where step number one is to select “.3mf” format. (Image courtesy PADT)

You can select “.3mf” but don’t Save yet. First, click on the “Options” button that shows up below the Save as File Type line, opening this window:

Second step in SolidWorks for saving a file in 3MF format: check off “include materials” and “include appearance.” (Image courtesy PADT)

You need to check the boxes for “Include Materials” and “Include Appearances” to ensure that all that great information you specified in the solid model gets written to the converted file. A good, short tutorial can be found here.

Another interesting aspect of 3MF files is that they are zipped internally, and therefore smaller than STL files. Look at the difference in file size between the two formats when this ASA Omega Clip part is saved both ways:

Comparison of file size for STL versus 3MF formats.

The 3MF-saved file size is just 13% the size of the standard STL file, which may be significant for file manipulation; for files with a lot of detail such as texture information, the difference won’t be as great, but you can still expect to save 30 to 50%.

Working with 3MF files in GrabCAD Print

Okay, so CAD programs export files in 3MF format. The other half of the story addresses the question: how does a 3D printer import and use a 3MF file? Developers of 3D printing systems follow these same consortium specifications to define how their software will set up a 3MF file to print. Some slicers and equipment already act upon some of the expanded build information, while others may accept the file but still treat it the same as an STL (no additional functions enabled so it ignores the extra data). What matters is whether the system is itself capable of printing with multiple materials or depositing material in a way that adds color, texture, transparency or a variation in internal geometry.

GrabCAD Print (GCP), the cloud-connected 3D Printer interface for today’s Stratasys printers – both FDM and PolyJet – has always supported STL and native CAD file import. However, in GCP v.1.40, released in March 2020, GrabCAD has added support for 3MF files. For files created by SolidWorks software, this adds the ability to specify face colors, body colors and textures and send all that data in one file to a PolyJet multi-material, multi-color 3D printer. (Stratasys FDM printers accept 3MF geometry and assembly structure information.)

For a great tutorial about setting up SolidWorks models with applied appearances and sending their 3MF files to GrabCAD Print, check out these step-by-step directions from Shuvom Ghose.

Example of setting up a textured part in SolidWorks, then saving the file in 3MF format and importing it into GrabCAD Print, for printing on a full-color Stratasys PolyJet printer. (Image courtesy GrabCAD)

Example of setting up a textured part in SolidWorks, then saving the file in 3MF format and importing it into GrabCAD Print, for printing on a full-color Stratasys PolyJet printer. (Image courtesy GrabCAD)

At PADT, we’re starting to learn the nuances of working with 3MF files and will be sharing more examples soon. In the meantime, we suggest you download your own free copy of GrabCAD Print to check out the new capabilities, then email or call us to learn more.

PADT Inc. is a globally recognized provider of Numerical Simulation, Product Development and 3D Printing products and services. For more information on Stratasys printers and materials, contact us at

Optimizing Materials Selection for Additive with ANSYS Granta – Webinar

There are hundreds of industrial AM machines and materials. New products come to market weekly, and picking the best option for a manufacturing or research project is a tough call. A wrong direction can be costly. This is where Ansys Granta and the Senvol Database come in handy. 

The Senvol Database details 1,000 AM machines and more than 850 compatible materials. Using this tool within Granta Selector, you can search and compare materials based on properties, type, or compatible machines. Identify and compare machines based on supported processes, manufacturer, required part size, cost, or compatible materials (and their properties). Quickly focus on the most likely routes to achieve project goals, save time and get new ideas as you research AM options.

Join PADT’s Application Engineer Robert McCathren for an overview of Ganta Material Selector, along with its importance and applications for those working with or interested in additive manufacturing.

Register Here

If this is your first time registering for one of our Bright Talk webinars, simply click the link and fill out the attached form. We promise that the information you provide will only be shared with those promoting the event (PADT).

You will only have to do this once! For all future webinars, you can simply click the link, add the reminder to your calendar and you’re good to go!

All Things Ansys 061: Bring Your Simulation Home with Ansys Cloud Solutions


Published on: April 20th, 2020
With: Eric Miller & Sina Ghods

In this episode your host and Co-Founder of PADT, Eric Miller is joined by PADT’s Senior Simulation Support & Application Engineer Sina Ghods for a look at what is new with Ansys Cloud and how the tool provides access to higher fidelity models, faster turnaround, and multiple supported solvers, anywhere and anytime.

If you would like to learn more about the Ansys tool offering access to simulation on the go, check out our webinar on the topic here:

If you have any questions, comments, or would like to suggest a topic for the next episode, shoot us an email at we would love to hear from you!



Making Sense of DC IR Results in Ansys SIwave

In this article I will cover a Voltage Drop (DC IR) simulation in SIwave, applying realistic power delivery setup on a simple 4-layer PCB design. The main goal for this project is to understand what data we receive by running DC IR simulation, how to verify it, and what is the best way of using it.

And before I open my tools and start diving deep into this topic, I would like to thank Zachary Donathan for asking the right questions and having deep meaningful technical discussions with me on some related subjects. He may not have known, but he was helping me to shape up this article in my head!

Design Setup

There are many different power nets present on the board under test, however I will be focusing on two widely spread nets +1.2V and +3.3V. Both nets are being supplied through Voltage Regulator Module (VRM), which will be assigned as a Voltage Source in our analysis. After careful assessment of the board design, I identified the most critical components for the power delivery to include in the analysis as Current Sources (also known as ‘sinks’). Two DRAM small outline integrated circuit (SOIC) components D1 and D2 are supplied with +1.2V. While power net +3.3V provides voltage to two quad flat package (QFP) microcontrollers U20 and U21, mini PCIE connector, and hex Schmitt-Trigger inverter U1.

Fig. 1. Power Delivery Network setting for a DC IR analysis

Figure 1 shows the ‘floor plan’ of the DC IR analysis setup with 1.2V voltage path highlighted in yellow and 3.3V path highlighted in light blue.

Before we assign any Voltage and Current sources, we need to define pin groups for all nets +1.2V, +3.3V and GND for all PDN component mentioned above. Having pin groups will significantly simplify the reviewing process of the results. Also, it is generally a good practice to start the DC IR analysis from the ‘big picture’ to understand if certain component gets enough power from the VRM. If a given IC reports an acceptable level of voltage being delivered with a good margin, then we don’t need to dig deeper; we can instead focus on those which may not have good enough margins.

Once we have created all necessary pin groups, we can assign voltage and current sources. There are several ways of doing that (using wizard or manual), for this project we will use ‘Generate Circuit Element on Components’ feature to manually define all sources. Knowing all the components and having pin groups already created makes the assignment very straight-forward. All current sources draw different amount of current, as indicated in our setting, however all current sources have the same Parasitic Resistance (very large value) and all voltage source also have the same Parasitic Resistance (very small value). This is shown on Figure 2 and Figure 3.

Note: The type of the current source ‘Constant Voltage’ or ‘Distributed Current’ matters only if you are assigning a current source to a component with multiple pins on the same net, and since in this project we are working with pins groups, this setting doesn’t make difference in final results.

Fig. 2. Voltage and Current sources assigned
Fig. 3. Parasitic Resistance assignments for all voltage and current sources

For each power net we have created a voltage source on VRM and multiple current sources on ICs and the connector. All sources have a negative node on a GND net, so we have a good common return path. And in addition, we have assigned a negative node of both voltage sources (one for +1.2V and one for +3.3V) as our reference points for our analysis. So reported voltage values will be referenced to that that node as absolute 0V.

At this point, the DC IR setup is complete and ready for simulation.

Results overview and validation

When the DC IR simulation is finished, there is large amount of data being generated, therefore there are different ways of viewing results, all options are presented on Figure 4. In this article I will be primarily focusing on ‘Power Tree’ and ‘Element Data’. As an additional source if validation we may review the currents and voltages overlaying the design to help us to visualize the current flow and power distribution. Most of the time this helps to understand if our assumption of pin grouping is accurate.

Fig. 4. Options to view different aspects of DC IR simulated data

Power Tree

First let’s look at the Power Tree, presented on Figure 5. Two different power nets were simulated, +1.2V and +3.3V, each of which has specified Current Sources where the power gets delivered. Therefore, when we analyze DC IR results in the Power tree format, we see two ‘trees’, one for each power net. Since we don’t have any pins, which would get both 1.2V and 3.3V at the same time (not very physical example), we don’t have ‘common branches’ on these two ‘trees’.

Now, let’s dissect all the information present in this power tree (taking in consideration only one ‘branch’ for simplicity, although the logic is applicable for all ‘branches’):

  • We were treating both power nets +1.2V and +3.3V as separate voltage loops, so we have assigned negative nodes of each Voltage Source as a reference point. Therefore, we see the ‘GND’ symbol ((1) and (2)) for each voltage source. Now all voltage calculations will be referenced to that node as 0V for its specific tree.
  • Then we see the path from Voltage Source to Current Source, the value ΔV shows the Voltage Drop in that path (3). Ultimately, this is the main value power engineers usually are interested in during this type of analysis. If we subtract ΔV from Vout we will get the ‘Actual Voltage’ delivered to the specific current source positive pin (1.2V – 0.22246V = 0.977V). That value reported in the box for the Current Source (4). Technically, the same voltage drop value is reported in the column ‘IR Drop’, but in this column we get more details – we see what the percentage of the Vout is being dropped. Engineers usually specify the margin value of the acceptable voltage drop as a percentage of Vout, and in our experiment we have specified 15%, as reported in column ‘Specification’. And we see that 18.5% is greater than 15%, therefore we get ‘Fail_I_&_V’ results (6) for that Current Source.
  • Regarding the current – we have manually specified the current value for each Current Source. Current values in Figure 2 are the same as in Figure 5. Also, we can specify the margin for the current to report pass or fail. In our example we assigned 108A as a current at the Current Source (5), while 100A is our current limit (4). Therefore, we also got failed results for the current as well.
  • As mentioned earlier, we assigned current values for each Current Source, but we didn’t set any current values for the Voltage Source. This is because the tool calculates how much current needs to be assigned for the Voltage Source, based on the value at the Current Sources. In our case we have 3 Current Sources 108A, 63A, 63A (5). The sum of these three values is 234A, which is reported as a current at the Voltage Source (7). Later we will see that this value is being used to calculate output power at the Voltage Source.  
Fig. 5. DC IR simulated data viewed as a ‘Power Tree’

Element Data

This option shows us results in the tabular representation. It lists many important calculated data points for specific objects, such as bondwire, current sources, all vias associated with the power distribution network, voltage probes, voltage sources.

Let’s continue reviewing the same power net +1.2V and the power distribution to CPU1 component as we have done for Power Tree (Figure 5). The same way we will be going over the details in point-by-point approach:

  • First and foremost, when we look at the information for Current Sources, we see a ‘Voltage’ value, which may be confusing. The value reported in this table is 0.7247V (8), which is different from the reported value of 0.977V in Power Tree on Figure 5 (4). The reason for the difference is that reported voltage value were calculated at different locations. As mentioned earlier, the reported voltage in the Power Tree is the voltage at the positive pin of the Current Source. The voltage reported in Element Data is the voltage at the negative pin of the Current Source, which doesn’t include the voltage drop across the ground plane of the return path.

To verify the reported voltage values, we can place Voltage Probes (under circuit elements). Once we do that, we will need to rerun the simulation in order to get the results for the probes:

  1. Two terminals of the ‘VPROBE_1’ attached at the positive pin of Voltage Source and at the positive pin of the Current Source. This probe should show us the voltage difference between VRM and IC, which also the same as reported Voltage Drop ΔV. And as we can see ‘VPROBE_1’ = 222.4637mV (13), when ΔV = 222.464mV (3). Correlated perfectly!
  2. Two terminals of the ‘VPROBE_GND’ attached to the negative pin of the Current Source and negative pin of the Voltage Source. The voltage shown by this probe is the voltage drop across the ground plane.

If we have 1.2V at the positive pin of VRM, then voltage drops 222.464mV across the power plane, so the positive pin of IC gets supplied with 0.977V. Then the voltage at the Current Source 0.724827V (8) being drawn, leaving us with (1.2V – 0.222464V – 0.724827V) = 0.252709V at the negative pin of the Current Source. On the return path the voltage drops again across the ground plane 252.4749mV (14) delivering back at the negative pin of VRM (0.252709V – 0.252475V) = 234uV. This is the internal voltage drop in the Voltage Source, as calculated as output current at VRM 234A (7) multiplied by Parasitic Resistance 1E-6Ohm (Figure 3) at VRM. This is Series R Voltage (11)

  • Parallel R Current of the Current source is calculated as Voltage 724.82mV (8) divided by Parasitic Resistance of the Current Source (Figure 3) 5E+7 Ohm = 1.44965E-8 (9)
  • Current of the Voltage Source report in the Element Data 234A (10) is the same value as reported in the Power Tree (sum of all currents of Current Sources for the +1.2V power net) = 234A (7). Knowing this value of the current we can multiple it by Parasitic Resistance of the Voltage Source (Figure 3) 1E-6 Ohm = (234A * 1E-6Ohm) = 234E-6V, which is equal to reported Series R Voltage (11). And considering that the 234A is the output current of the Voltage Source, we can multiple it by output voltage Vout = 1.2V to get a Power Output = (234A * 1.2V) = 280.85W (12)
Fig. 6. DC IR simulated data viewed in the table format as ‘Element Data’

In addition to all provided above calculations and explanations, the video below in Figure 7 highlights all the key points of this article.

Fig. 7. Difference between reporting Voltage values in Power Tree and Element Data


By carefully reviewing the Power Tree and Element Data reporting options, we can determine many important decisions about the power delivery network quality, such as how much voltage gets delivered to the Current Source; how much voltage drop is on the power net and on the ground net, etc. More valuable information can be extracted from other DC IR results options, such as ‘Loop Resistance’, ‘Path Resistance’, ‘RL table’, ‘Spice Netlist’, full ‘Report’. However, all these features deserve a separate topic.

As always, if you would like to receive more information related to this topic or have any questions please reach out to us at

Bring Your Simulation Home with Ansys Cloud Solutions – Webinar

Engineering simulation has long been constrained by fixed computing resources available on a desktop or cluster. Today, however, cloud computing can deliver the on-demand, high performance computing (HPC) capacity required for faster high-fidelity results offering greater performance insight, all from the comfort of your home.

Ansys Cloud delivers the speed, power and compute capacity of cloud computing directly to your desktop — when and where you need it. You can run larger, more complex and more accurate simulations to gain more insight into your product — or you can evaluate more design variations to find the optimal design without long hardware/software procurement and deployment delays.

Join PADT’s Senior Application & Simulation Support Engineer Sina Ghods for a look at how Ansys is working to drive adoption by providing users a ready to use cloud service that provides:

  • Higher Fidelity Models
  • Faster Turnaround Time
  • Improved Productivity
  • Flexible Licensing
  • Multiple Supported Solvers
  • And Much More

Register Here

If this is your first time registering for one of our Bright Talk webinars, simply click the link and fill out the attached form. We promise that the information you provide will only be shared with those promoting the event (PADT).

You will only have to do this once! For all future webinars, you can simply click the link, add the reminder to your calendar and you’re good to go!

All Things Ansys 060: Tips For Making Working From Home More Productive


Published on: April 6th, 2020
With: Eric Miller & Matt Sutton

In this episode your host and Co-Founder of PADT, Eric Miller is joined by PADT’s seasoned expert at working with Ansys from home Matt Sutton for a quick discussion on tips and best practices that make working from home more productive and effective.

If you would like to learn more about how PADT and Ansys can help you to better run your simulation from your home office, check out our webinar on the topic here:

If you have any questions, comments, or would like to suggest a topic for the next episode, shoot us an email at we would love to hear from you!



Efficient and Accurate Simulation of Antenna Arrays in Ansys HFSS

Unit-cell in HFSS

HFSS offers different method of creating and simulating a large array. The explicit method, shown in Figure 1(a) might be the first method that comes to our mind. This is where you create the exact CAD of the array and solve it. While this is the most accurate method of simulating an array, it is computationally extensive. This method may be non-feasible for the initial design of a large array. The use of unit cell (Figure 1(b)) and array theory helps us to start with an estimate of the array performance by a few assumptions. Finite Array Domain Decomposition (or FADDM) takes advantage of unit cell simplicity and creates a full model using the meshing information generated in a unit cell. In this blog we will review the creation of unit cell. In the next blog we will explain how a unit cell can be used to simulate a large array and FADDM.

Fig. 1 (a) Explicit Array
Fig. 1 (b) Unit Cell
Fig. 1 (c) Finite Array Domain Decomposition (FADDM)

In a unit cell, the following assumptions are made:

  • The pattern of each element is identical.
  • The array is uniformly excited in amplitude, but not necessarily in phase.
  • Edge affects and mutual coupling are ignored
Fig. 2 An array consisting of elements amplitude and phases can be estimated with array theory, assuming all elements have the same amplitude and element radiation patterns. In unit cell simulation it is assumed all magnitudes (An’s) are equal (A) and the far field of each single element is equal.

A unit cell works based on Master/Slave (or Primary/Secondary) boundary around the cell. Master/Slave boundaries are always paired. In a rectangular cell you may use the new Lattice Pair boundary that is introduced in Ansys HFSS 2020R1. These boundaries are means of simulating an infinite array and estimating the performance of a relatively large arrays. The use of unit cell reduces the required RAM and solve time.

Primary/Secondary (Master/Slave) (or P/S) boundaries can be combined with Floquet port, radiation or PML boundary to be used in an infinite array or large array setting, as shown in Figure 3.

Fig. 3 Unit cell can be terminated with (a) radiation boundary, (b) Floquet port, (c) PML boundary, or combination of them.

To create a unit cell with P/S boundary, first start with a single element with the exact dimensions of the cell. The next step is creating a vacuum or airbox around the cell. For this step, set the padding in the location of P/S boundary to zero. For example, Figure 4 shows a microstrip patch antenna that we intend to create a 2D array based on this model. The array is placed on the XY plane. An air box is created around the unit cell with zero padding in X and Y directions.

Fig. 4 (a) A unit cell starts with a single element with the exact dimensions as it appears in the lattice
Fig. 4 (b) A vacuum box is added around it

You notice that in this example the vacuum box is larger than usual size of quarter wavelength that is usually used in creating a vacuum region around the antenna. We will get to calculation of this size in a bit, for now let’s just assign a value or parameter to it, as it will be determined later. The next step is to define P/S to generate the lattice. In AEDT 2020R1 this boundary is under “Coupled” boundary. There are two methods to create P/S: (1) Lattice Pair, (2) Primary/Secondary boundary.

Lattice Pair

The Lattice Pair works best for square lattices. It automatically assigns the primary and secondary boundaries. To assign a lattice pair boundary select the two sides that are supposed to create infinite periodic cells, right-click->Assign Boundary->Coupled->Lattice Pair, choose a name and enter the scan angles. Note that scan angles can be assigned as parameters. This feature that is introduced in 2020R1 does not require the user to define the UV directions, they are automatically assigned.

Fig. 5 The lattice pair assignment (a) select two lattice walls
Fig. 5 (b) Assign the lattice pair boundary
Fig. 5 (c) After, right-click and choosing assign boundary > choose Lattice Pair
Fig. 5 (d) Phi and Theta scan angles can be assigned as parameters


Primary/Secondary boundary is the same as what used to be called Master/Slave boundary. In this case, each Secondary (Slave) boundary should be assigned following a Primary (Master) boundary UV directions. First choose the side of the cell that Primary boundary. Right-click->Assign Boundary->Coupled->Primary. In Primary Boundary window define U vector. Next select the secondary wall, right-click->Assign Boundary->Couple->Secondary, choose the Primary Boundary and define U vector exactly in the same direction as the Primary, add the scan angles (the same as Primary scan angles)

Fig. 6 Primary and secondary boundaries highlights.

Floquet Port and Modes Calculator

Floquet port excites and terminates waves propagating down the unit cell. They are similar to waveguide modes. Floquet port is always linked to P/S boundaries. Set of TE and TM modes travel inside the cell. However, keep in mind that the number of modes that are absorbed by the Floquet port are determined by the user. All the other modes are short-circuited back into the model. To assign a Floquet port two major steps should be taken:

Defining Floquet Port

Select the face of the cell that you like to assign the Floquet port. This is determined by the location of P/S boundary. The lattice vectors A and B directions are defined by the direction of lattice (Figure 7).

Fig. 7 Floquet port on top of the cell is defined based on UV direction of P/S pairs

The number of modes to be included are defined with the help of Modes Calculator. In the Mode Setup tab of the Floquet Port window, choose a high number of modes (e.g. 20) and click on Modes Calculator. The Mode Table Calculator will request your input of Frequency and Scan Angles. After selecting those, a table of modes and their attenuation using dB/length units are created. This is your guide in selecting the height of the unit cell and vaccume box. The attenation multiplied by the height of the unit cell (in the project units, defined in Modeler->Units) should be large enough to make sure the modes are attenuated enough so removing them from the calcuatlion does not cause errors. If the unit cell is too short, then you will see many modes are not attenuated enough. The product of the attenuatin and height of the airbox should be at least 50 dB. After the correct size for the airbox is calcualted and entered, the model with high attenuation can be removed from the Floquet port definition.

The 3D Refinement tab is used to control the inclusion of the modes in the 3D refinement of the mesh. It is recommended not to select them for the antenna arrays.

Fig. 8 (Left) Determining the scan angles for the unit cell, (Right) Modes Calculator showing the Attenuation

In our example, Figure 8 shows that the 5th mode has an attenuation of 2.59dB/length. The height of the airbox is around 19.5mm, providing 19.5mm*2.59dB/mm=50.505dB attenuation for the 5th mode. Therefore, only the first 4 modes are kept for the calculations. If the height of the airbox was less than 19.5mm, we would need to increase the height so accordingly for an attenuation of at least 50dB.

Radiation Boundary

A simpler alternative for Floquet port is radiation boundary. It is important to note that the size of the airbox should still be kept around the same size that was calculated for the Floquet port, therefore, higher order modes sufficiently attenuated. In this case the traditional quarter wavelength padding might not be adequate.

Fig. 9 Radiation boundary on top of the unit cell

Perfectly Matched Layer

Although using radiation boundary is much simpler than Floquet port, it is not accurate for large scan angles. It can be a good alternative to Floquet port only if the beam scanning is limited to small angles. Another alternative to Floquet port is to cover the cell by a layer of PML. This is a good compromise and provides very similar results to Floquet port models. However, the P/S boundary need to surround the PML layer as well, which means a few additional steps are required. Here is how you can do it:

  1. Reduce the size of the airbox* slightly, so after adding the PML layer, the unit cell height is the same as the one that was generated using the Modes Calculation. (For example, in our model airbox height was 19mm+substrte thickness, the PML height was 3mm, so we reduced the airbox height to 16mm).
  2. Choose the top face and add PML boundary.
  3. Select each side of the airbox and create an object from that face (Figure 10).
  4. Select each side of the PML and create objects from those faces (Figure 10).
  5. Select the two faces that are on the same plane from the faces created from airbox and PML and unite them to create a side wall (Figure 10).
  6. Then assign P/S boundary to each pair of walls (Figure 10).

*Please note for this method, an auto-size “region” cannot be used, instead draw a box for air/vacuum box. The region does not let you create the faces you need to combine with PML faces.

Fig. 10 Selecting two faces created from airbox and PML and uniting them to assign P/S boundaries

The advantage of PML termination over Floquet port is that it is simpler and sometimes faster calculation. The advantage over Radiation Boundary termination is that it provides accurate results for large scan angles. For better accuracy the mesh for the PML region can be defined as length based.

Seed the Mesh

To improve the accuracy of the PML model further, an option is to use length-based mesh. To do this select the PML box, from the project tree in Project Manager window right-click on Mesh->Assign Mesh Operation->On Selection->Length Based. Select a length smaller than lambda/10.

Fig. 11 Using element length-based mesh refinement can improve the accuracy of PML design

Scanning the Angle

In phased array simulation, we are mostly interested in the performance of the unit cell and array at different scan angles. To add the scanning option, the phase of P/S boundary should be defined by project or design parameters. The parameters can be used to run a parametric sweep, like the one shown in Figure 12. In this example the theta angle is scanned from 0 to 60 degrees.

Fig. 12 Using a parametric sweep, the scanned patterns can be generated

Comparing PML and Floquet Port with Radiation Boundary

To see the accuracy of the radiation boundary vs. PML and Floquet Port, I ran the simulations for scan angles up to 60 degrees for a single element patch antenna. Figure 13 shows that the accuracy of the Radiation boundary drops after around 15 degrees scanning. However, PML and Floquet port show similar performance.

Fig. 13 Comparison of radiation patterns using PML (red), Floquet Port (blue), and Radiation boundary (orange).

S Parameters

To compare the accuracy, we can also check the S parameters. Figure 14 shows the comparison of active S at port 1 for PML and Floquet port models. Active S parameters were used since the unit cell antenna has two ports. Figure 15 shows how S parameters compare for the model with the radiation boundary and the one with the Floquet port.

Fig. 14 Active S parameter comparison for different scan angles, PML vs. Floquet Port model.
Fig. 15 Active S parameter comparison for different scan angles, Radiation Boundary vs. Floquet Port model.


The unit cell definition and options on terminating the cell were discussed here. Stay tuned. In the next blog we discuss how the unit cell is utilized in modeling antenna arrays.

Test, Design & Analyze From Home With Ansys Simulation Software – Webinar

As companies are closing their doors in order to help ensure the health and safety of their employees and customers, those that can are pivoting to working form home. Tadam black stock is one of the best guide.

But what about those working on product design, testing, and analysis that require a physical presence?

Here at PADT we know that the show must go on, and companies working across various technical professions are needed to keep the world moving forward, especially in these trying times. Thus we would like to introduce a solution: Ansys Engineering Simulation Software. You can also visit cherryscustomframing to know more.

Join The PADT team for a panel discussion on how you can use simulation to move your in-person workflow to a digital environment, as well as what specific Ansys tools can be used to access your work from home.

All of this will be followed by a live Q&A in which our expert staff will take any questions regarding your specific concerns with transitioning your workflow and all other things related to working from home.

Register Here

If this is your first time registering for one of our Bright Talk webinars, simply click the link and fill out the attached form. We promise that the information you provide will only be shared with those promoting the event (PADT).

You will only have to do this once! For all future webinars, you can simply click the link, add the reminder to your calendar and you’re good to go!

Ansys Sherlock: A Comprehensive Electronics Reliability Tool

As systems become more complex, the introduction and adoption of detailed Multiphysics / Multidomain tools is becoming more commonplace. Oftentimes, these tools serve as preprocessors and specialized interfaces for linking together other base level tools or models in a meaningful way. This is what Ansys Sherlock does for Circuit Card Assemblies (CCAs), with a heavy emphasis on product reliability through detailed life cycle definitions.

In an ideal scenario, the user will have already compiled a detailed ODB++ archive containing all the relevant model information. For Sherlock, this includes .odb files for each PCB layer, the silkscreens, component lists, component locations separated by top/bottom surface, drilled locations, solder mask maps, mounting points, and test points. This would provide the most streamlined experience from a CCA design through reliability analysis, though any of these components can be imported individually.

These definitions, in combination with an extensive library of package geometries, allow Sherlock to generate a 3D model consisting of components that can be checked against accepted parts lists and material properties. The inclusion of solder mask and silkscreen layers also makes for convenient spot-checking of component location and orientation. If any of these things deviate from the expected or if basic design variation and optimization studies need to be conducted, new components can be added and existing components can be removed, exchanged, or edited entirely within Sherlock.

Figure 1: Sherlock’s 2D layer viewer and editor. Each layer can be toggled on/off, and components can be rearranged.

While a few of the available analyses depend on just the component definitions and geometries (Part Validation, DFMEA, and CAF Failure), the rest are in some way connected to the concept of life cycle definitions. The overall life cycle can be organized into life phases, e.g. an operating phase, packaging phase, transport phase, or idle phase, which can then contain any number of unique event definitions. Sherlock provides support for vibration events (random and harmonic), mechanical shock events, and thermal events. At each level, these phases and events can be prescribed a total duration, cycle count, or duty cycle relative to their parent definition. On the Life Cycle definition itself, the total lifespan and accepted failure probability within that lifespan are defined for the generation of final reliability metrics.  Figure 1 demonstrates an example layout for a CCA that may be part of a vehicle system containing both high cycle fatigue thermal and vibration events, and low cycle fatigue shock events.

Figure 2: Product life cycles are broken down into life phases that contain life events. Each event is customizable through its duration, frequency, and profile.

The remaining analysis types can be divided into two categories: FEA and part specification-based. The FEA based tests function by generating a 3D model with detail and mesh criteria determined within Sherlock, which is then passed over to an Ansys Mechanical session for analysis. Sherlock provides quite a lot of customization on the pre-processing level; the menu options include different methods and resolutions for the PCB, explicit modeling of traces, and inclusion or exclusion of part leads, mechanical parts, and potting regions, among others.

Figure 3: Left shows the 3D model options, the middle shows part leads modeled, and right shows a populated board.

Each of the FEA tests, Random Vibration, Harmonic Vibration, Mechanical Shock, and Natural Frequency, correspond to an analysis block within Ansys Workbench. Once these simulations are completed, the results file is read back into Sherlock, and strain values for each component are extracted and applied to either Basquin or Coffin—Manson fatigue models as appropriate for each included life cycle event.

Part specification tests include Component Failure Analysis for electrolytic and ceramic capacitors, Semiconductor Wearout for semiconductor devices, and CTE mismatch issues for Plated Through-Hole and solder fatigue. These analyses are much more component-specific in the sense that an electrolytic capacitor has some completely different failure modes than a semiconductor device and including them allows for a broad range of physics to be accounted for across the CCA.

The result from each type of analysis is ultimately a life prediction for each component in terms of a failure probability curve alongside a time to failure estimate. The curves for every component are then combined into a life prediction for the entire CCA under one failure analysis.

Figure 4: Analysis results for Solder Fatigue including an overview for quantity of parts in each score range along with a detailed breakdown of score for each board component.

Taking it one step further, the results from each analysis are then combined into an overall life prediction for the CCA that encompasses all the defined life events. From Figure 5, we can see that the life prediction for this CCA does not quite meet its 5-year requirement, and that the most troublesome analyses are Solder Fatigue and PTH Fatigue. Since Sherlock makes it easy to identify these as problem areas, we could then iterate on this design by reexamining the severity or frequency of applied thermal cycles or adjusting some of the board material choices to minimize CTE mismatch.

Figure 5: Combined life predictions for all failure analyses and life events.

Sherlock’s convenience for defining life cycle phases and events, alongside the wide variety of component definitions and failure analyses available, really cement Sherlock’s role as a comprehensive electronics reliability tool. As in most analyses, the quality of the results is still dependent on the quality of the input, but all the checks and cross-validations for components vs life events that come along with Sherlock’s preprocessing toolset really assist with this, too.