The world of additive manufacturing, or 3D printing, is constantly evolving. The technology was invented less than 35 years ago yet has come a long way. What began as a unique, though limited, way to develop low-end prototypes, has exploded into a critical component of the product development and manufacturing process with the ability to produce end-use parts for critical applications in markets such as industrial and aerospace and defense.
To help our customers and the larger technology community stay abreast of the changing world of additive manufacturing, we launched a glossary of the most important terms in the industry that you can bookmark here for easy access. To make it easier to digest, we’re also starting a blog series outlining ten terms to know in different sub-categories.
For our first post in the series, here are the top ten terms
for Additive Manufacturing Processes that our experts think everyone
should know:
Any additive manufacturing process that uses a binder to
chemically bond powder where the binder is placed on the top layer of powder
through small jets, usually using inkjet technology. One of the seven standard
categories defined by ASTM International (www.ASTM.org) for additive
manufacturing processes.
A type of vat photopolymerization additive
manufacturing process where a projector under a transparent build
plate shines ultraviolet light onto the build layer, which
is against the transparent build plate. The part is then pulled
upward so that a new layer of liquid fills between the build
plate and the part, and the process is repeated. Digital light
synthesis is a continuous build process that does not create distinct layers.
A type of powder bed fusion additive manufacturing
process where a laser beam is used to melt powder material. The
beam is directed across the top layer of powder. The liquid material
solidifies to create the desired part. A new layer of powder is
placed on top, and the process is repeated. Also called laser powder bed
fusion, metal powder bed fusion, or direct metal laser sintering.
An additive manufacturing process where metal
powder is jetted, or wire is extruded from a CNC controlled three or
five-axis nozzle. The solid material is then melted by an energy source,
usually a laser or electron beam, such that the liquid metal
deposits onto the previous layers (or build plate) and then cools to a
solid. One of the ASTM defined standard categories for additive
manufacturing processes.
A type of material extrusion additive manufacturing process
where a continuous filament of thermoplastic material is fed into a heated
extruder and deposited on the current build layer. It is the trademarked name
used for systems manufactured by the process inventor, Stratasys. Fused
filament fabrication is the generic term.
A type of powder bed fusion additive
manufacturing process where a laser is used to melt material on
the top layer of a powder bed. Also called metal powder bed
fusion or direct laser melting. Most often used to melt metal powder
but is used with plastics as with selective laser sintering.
A type of direct energy deposition additive
manufacturing process where a powder is directed into a
high-energy laser beam and melted before it is deposited on
the build layer. Also called laser powder forming.
Any additive manufacturing process where build
or support material is jetted through multiple small nozzles whose
position is computer controlled to lay down material to create a layer.
One of the ASTM defined standard categories for additive
manufacturing processes.
A type of vat photopolymerization additive
manufacturing where a laser is used to draw a path on the
current layer, converting the liquid polymer into a solid. Stereolithography
was the first commercially available additive manufacturing process.
A class of additive manufacturing processes that utilizes
the hardening of a photopolymer with ultraviolet light. A vat of liquid is
filled with liquid photopolymer resin, and ultraviolet light is either traced
on the build surface or projected on it. Stereolithography is the most common
form of vat photopolymerization. The build layer can be on the top of the vat
of liquid or the bottom. One of the ASTM defined standard categories for
additive manufacturing processes.
We hope this new blog series will help to firm up your
knowledge of the ever-evolving world of additive manufacturing. For a list of
all of the key terms and definitions in the additive manufacturing world,
please visit our new glossary page at https://www.3dprinting-glossary.com/.
The glossary allows you to search by terms or download a PDF of the glossary in
its entirety to use as a reference guide.
Subscribe to the
PADT blog or check back soon for the next installment in our series of “Top Ten
Terms to Know in Additive Manufacturing.” We also welcome your feedback or
questions. Just drop us a line at here.
In this episode your host and Co-Founder of PADT, Eric Miller is joined by PADT’s systems application & support engineer Josh Stout to look at the optimization tool optiSLang. This tool helps automate simulation and optimization activities across various solution areas, such as autonomy, electrification, digital twins, and more, as well as how it enables users to capitalize on the benefits of enterprise simulation management.
If you would like to learn more, you can view the product brochure here: https://www.ansys.com/-/media/ansys/corporate/resourcelibrary/brochure/optislang-brochure.pdf.
If you have any questions, comments, or would like to suggest a topic for the next episode, shoot us an email at podcast@padtinc.com we would love to hear from you!
Advatech Pacific, a Phoenix-based aerospace and defense contractor founded in 1995, works to change the way engineering is conducted for the better by incorporating innovative technologies into its customer’s workflow. Based on the success of previous projects, Advatech is a strong proponent of using high-end simulation software such as Ansys to identify and evaluate the fine details of massive multi-body mechanical systems, whether through simple static analyses or tightly-coupled multiphysics computations.
Implementing additive manufacturing as an additional way to improve system design presented opportunities to cut back on tooling costs and reduce lead time for several candidate turbine-engine parts. Doing so would also alleviate the challenge of reproducing complex castings, a problem made increasingly difficult by the fact that many of the original casting providers are no longer in business.
Join PADT’s Lead Mechanical Engineer Doug Oatis, and Advatech Pacific’s Engineering Manager Matt Humrick for a discussion on Ansys tools with regards to additive manufacturing & topology optimization, and how Advatech Pacific was able to use them to drastically improve the efficiency of their design and manufacturing process.
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In this episode your host and Co-Founder of PADT, Eric Miller is joined by Ansys CMO Lynn Ledwith, for a look at their digital trade show, Simulation world taking place Wednesday June 10th through Thursday June 11th.
The largest engineering simulation virtual event in the world, this event is a free online conference designed to inspire and educate executives, engineers, R&D, and manufacturing professionals about the transformative powers of engineering simulation and Ansys.
If you would like to learn more, visit simulation-world.com or register for free via https://bit.ly/2XjxrCN
If you have any questions, comments, or would like to suggest a topic for the next episode, shoot us an email at podcast@padtinc.com we would love to hear from you!
Simulation has been and continues to be a powerful tool for helping to drive innovation in the medical industry. Everything from medical devices, to hospital equipment, and even pharmaceutical and clinical practices can benefit from the introduction of simulation technology. This is true now more than ever, as the we all are facing such turbulent times.
During the COVID-19 pandemic, Ansys is striving to combat the spread of the coronavirus, by backing the ongoing initiatives of customers and partners working in the medical sphere. In order to support healthcare professionals, policy makers, and communities around the world in this endeavor, Ansys is sharing key insights gained from their own analyse, along with those of partners and other collaborators, regarding how to prevent future spread, and treat those already effected by the virus.
Join PADT’s Co-founder and Principal engineer Eric Miller, along with Marc Horner, Principal Healthcare Engineer at Ansys, for a discussion on what the company is doing to combat the virus, as well as a look at some models that effectively illustrate how the tools are being used.
In 2017 Colorado based company Ursa Major Technologies put together an expert team of designers and engineers to realize its vision of providing the microsatellite industry with the best rocket engines in the business. Utilizing Ansys simulation software, additive manufacturing, and modernizing staged combustion, the company successfully designed and built two liquid oxygen and kerosene engines and has a third engine in development.
With Ansys, Ursa Major Technologies is accomplishing design goals faster and more efficiently than ever before. Using Finite Element Analysis (FEA), the company can run models with 30-40 unique parts to analyze entire turbo pumps in one simulation. Thrust analysis, which the company had previously done with 2D models, can now be done all in the Ansys CFX tool more cost-effectively.
JoinPADT and Ursa Major Technologies for a brief overview of applications for Ansys in the aerospace industry, followed by an exploration of how they are using these simulation tools to better design and optimize the next generation of rocket engines.
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You will only have to do this once! For all future webinars, you can simply click the link, add the reminder to your calendar and you’re good to go!
In this episode your host and Co-Founder of PADT, Eric Miller is joined by PADT’s Senior Simulation Support & Application Engineer Sina Ghods for a look at what is new with Ansys Cloud and how the tool provides access to higher fidelity models, faster turnaround, and multiple supported solvers, anywhere and anytime.
If you would like to learn more about the Ansys tool offering access to simulation on the go, check out our webinar on the topic here: https://bit.ly/3al5PjH
If you have any questions, comments, or would like to suggest a topic for the next episode, shoot us an email at podcast@padtinc.com we would love to hear from you!
In this article I will cover a Voltage Drop (DC IR) simulation in SIwave, applying realistic power delivery setup on a simple 4-layer PCB design. The main goal for this project is to understand what data we receive by running DC IR simulation, how to verify it, and what is the best way of using it.
And before I open my tools and start diving deep into this topic, I would like to thank Zachary Donathan for asking the right questions and having deep meaningful technical discussions with me on some related subjects. He may not have known, but he was helping me to shape up this article in my head!
Design Setup
There are many different power nets present on the board
under test, however I will be focusing on two widely spread nets +1.2V and
+3.3V. Both nets are being supplied through Voltage Regulator Module (VRM),
which will be assigned as a Voltage Source in our analysis. After careful
assessment of the board design, I identified the most critical components for
the power delivery to include in the analysis as Current Sources (also known as
‘sinks’). Two DRAM small outline integrated circuit (SOIC) components D1 and D2
are supplied with +1.2V. While power net +3.3V provides voltage to two quad
flat package (QFP) microcontrollers U20 and U21, mini PCIE connector, and hex
Schmitt-Trigger inverter U1.
Fig. 1. Power Delivery Network setting for a DC IR analysis
Figure 1 shows the ‘floor plan’ of the DC IR analysis
setup with 1.2V voltage path highlighted in yellow and 3.3V path highlighted in
light blue.
Before we assign any Voltage and Current sources, we need to
define pin groups for all nets +1.2V, +3.3V and GND for all PDN component
mentioned above. Having pin groups will significantly simplify the reviewing
process of the results. Also, it is generally a good practice to start the DC
IR analysis from the ‘big picture’ to understand if certain component gets
enough power from the VRM. If a given IC reports an acceptable level of voltage
being delivered with a good margin, then we don’t need to dig deeper; we can
instead focus on those which may not have good enough margins.
Once we have created all necessary pin groups, we can assign
voltage and current sources. There are several ways of doing that (using wizard
or manual), for this project we will use ‘Generate Circuit Element on
Components’ feature to manually define all sources. Knowing all the components
and having pin groups already created makes the assignment very
straight-forward. All current sources draw different amount of current, as indicated
in our setting, however all current sources have the same Parasitic Resistance
(very large value) and all voltage source also have the same Parasitic
Resistance (very small value). This is shown on Figure 2 and Figure 3.
Note: The type of the current source ‘Constant Voltage’ or
‘Distributed Current’ matters only if you are assigning a current source to a
component with multiple pins on the same net, and since in this project we are
working with pins groups, this setting doesn’t make difference in final results.
Fig. 2. Voltage and Current sources assigned
Fig. 3. Parasitic Resistance assignments for all voltage and current sources
For each power net we have created a voltage source on VRM and multiple current sources on ICs and the connector. All sources have a negative node on a GND net, so we have a good common return path. And in addition, we have assigned a negative node of both voltage sources (one for +1.2V and one for +3.3V) as our reference points for our analysis. So reported voltage values will be referenced to that that node as absolute 0V.
At this point, the DC IR setup is complete and ready for
simulation.
Results overview and validation
When the DC IR simulation is finished, there is large amount
of data being generated, therefore there are different ways of viewing results,
all options are presented on Figure 4. In this article I will be
primarily focusing on ‘Power Tree’ and ‘Element Data’. As an additional source
if validation we may review the currents and voltages overlaying the design to
help us to visualize the current flow and power distribution. Most of the time
this helps to understand if our assumption of pin grouping is accurate.
Fig. 4. Options to view different aspects of DC IR simulated data
Power Tree
First let’s look at the Power Tree, presented on Figure 5. Two different power nets were simulated, +1.2V and +3.3V, each of which has specified Current Sources where the power gets delivered. Therefore, when we analyze DC IR results in the Power tree format, we see two ‘trees’, one for each power net. Since we don’t have any pins, which would get both 1.2V and 3.3V at the same time (not very physical example), we don’t have ‘common branches’ on these two ‘trees’.
Now, let’s dissect all the information present in this power tree (taking in consideration only one ‘branch’ for simplicity, although the logic is applicable for all ‘branches’):
We were treating both power nets +1.2V and +3.3V as separate voltage loops, so we have assigned negative nodes of each Voltage Source as a reference point. Therefore, we see the ‘GND’ symbol ((1) and (2)) for each voltage source. Now all voltage calculations will be referenced to that node as 0V for its specific tree.
Then we see the path from Voltage Source to Current Source, the value ΔV shows the Voltage Drop in that path (3). Ultimately, this is the main value power engineers usually are interested in during this type of analysis. If we subtract ΔV from Vout we will get the ‘Actual Voltage’ delivered to the specific current source positive pin (1.2V – 0.22246V = 0.977V). That value reported in the box for the Current Source (4). Technically, the same voltage drop value is reported in the column ‘IR Drop’, but in this column we get more details – we see what the percentage of the Vout is being dropped. Engineers usually specify the margin value of the acceptable voltage drop as a percentage of Vout, and in our experiment we have specified 15%, as reported in column ‘Specification’. And we see that 18.5% is greater than 15%, therefore we get ‘Fail_I_&_V’ results (6) for that Current Source.
Regarding the current – we have manually specified the current value for each Current Source. Current values in Figure 2 are the same as in Figure 5. Also, we can specify the margin for the current to report pass or fail. In our example we assigned 108A as a current at the Current Source (5), while 100A is our current limit (4). Therefore, we also got failed results for the current as well.
As mentioned earlier, we assigned current values for each Current Source, but we didn’t set any current values for the Voltage Source. This is because the tool calculates how much current needs to be assigned for the Voltage Source, based on the value at the Current Sources. In our case we have 3 Current Sources 108A, 63A, 63A (5). The sum of these three values is 234A, which is reported as a current at the Voltage Source (7). Later we will see that this value is being used to calculate output power at the Voltage Source.
Fig. 5. DC IR simulated data viewed as a ‘Power Tree’
Element Data
This option shows us results in the tabular representation. It lists many important calculated data points for specific objects, such as bondwire, current sources, all vias associated with the power distribution network, voltage probes, voltage sources.
Let’s continue reviewing the same power net +1.2V and the power distribution to CPU1 component as we have done for Power Tree (Figure 5). The same way we will be going over the details in point-by-point approach:
First and foremost, when we look at the information for Current Sources, we see a ‘Voltage’ value, which may be confusing. The value reported in this table is 0.7247V (8), which is different from the reported value of 0.977V in Power Tree on Figure 5 (4). The reason for the difference is that reported voltage value were calculated at different locations. As mentioned earlier, the reported voltage in the Power Tree is the voltage at the positive pin of the Current Source. The voltage reported in Element Data is the voltage at the negative pin of the Current Source, which doesn’t include the voltage drop across the ground plane of the return path.
To verify the reported voltage values, we can place Voltage Probes (under circuit elements). Once we do that, we will need to rerun the simulation in order to get the results for the probes:
Two terminals of the ‘VPROBE_1’ attached at the positive pin of Voltage Source and at the positive pin of the Current Source. This probe should show us the voltage difference between VRM and IC, which also the same as reported Voltage Drop ΔV. And as we can see ‘VPROBE_1’ = 222.4637mV (13), when ΔV = 222.464mV (3). Correlated perfectly!
Two terminals of the ‘VPROBE_GND’ attached to the negative pin of the Current Source and negative pin of the Voltage Source. The voltage shown by this probe is the voltage drop across the ground plane.
If we have 1.2V at the positive pin of VRM, then voltage drops 222.464mV across the power plane, so the positive pin of IC gets supplied with 0.977V. Then the voltage at the Current Source 0.724827V (8) being drawn, leaving us with (1.2V – 0.222464V – 0.724827V) = 0.252709V at the negative pin of the Current Source. On the return path the voltage drops again across the ground plane 252.4749mV (14) delivering back at the negative pin of VRM (0.252709V – 0.252475V) = 234uV. This is the internal voltage drop in the Voltage Source, as calculated as output current at VRM 234A (7) multiplied by Parasitic Resistance 1E-6Ohm (Figure 3) at VRM. This is Series R Voltage (11)
Parallel R Current of the Current source is calculated as Voltage 724.82mV (8) divided by Parasitic Resistance of the Current Source (Figure 3) 5E+7 Ohm = 1.44965E-8 (9)
Current of the Voltage Source report in the Element Data 234A (10) is the same value as reported in the Power Tree (sum of all currents of Current Sources for the +1.2V power net) = 234A (7). Knowing this value of the current we can multiple it by Parasitic Resistance of the Voltage Source (Figure 3) 1E-6 Ohm = (234A * 1E-6Ohm) = 234E-6V, which is equal to reported Series R Voltage (11). And considering that the 234A is the output current of the Voltage Source, we can multiple it by output voltage Vout = 1.2V to get a Power Output = (234A * 1.2V) = 280.85W (12)
Fig. 6. DC IR simulated data viewed in the table format as ‘Element Data’
In addition to all provided above calculations and explanations, the video below in Figure 7 highlights all the key points of this article.
Fig. 7. Difference between reporting Voltage values in Power Tree and Element Data
Conclusion
By carefully reviewing the Power Tree and Element Data reporting options, we can determine many important decisions about the power delivery network quality, such as how much voltage gets delivered to the Current Source; how much voltage drop is on the power net and on the ground net, etc. More valuable information can be extracted from other DC IR results options, such as ‘Loop Resistance’, ‘Path Resistance’, ‘RL table’, ‘Spice Netlist’, full ‘Report’. However, all these features deserve a separate topic.
As always, if you would like to receive more information related to this topic or have any questions please reach out to us at info@padtinc.com.
In this episode your host and Co-Founder of PADT, Eric Miller is joined by PADT’s seasoned expert at working with Ansys from home Matt Sutton for a quick discussion on tips and best practices that make working from home more productive and effective.
If you would like to learn more about how PADT and Ansys can help you to better run your simulation from your home office, check out our webinar on the topic here: https://bit.ly/3dSa8WN
If you have any questions, comments, or would like to suggest a topic for the next episode, shoot us an email at podcast@padtinc.com we would love to hear from you!
Eric Miller, Ted Harris, Alex Grishin & Joe Woodward
Description:
In this episode your host and Co-Founder of PADT, Eric Miller is joined by PADT’s Ted Harris, Alex Grishin, and Joe Woodward to discuss their favorite features in the MAPDL Updates in Ansys 2020 R1.
If you would like to learn more about this topic, you can view PADT’s webinar covering these updates here: https://bit.ly/2WD88vt
Additionally, if you would like to take part in the survey mentioned at the start of the episode click the link here: https://bit.ly/3biWkCp
If you have any questions, comments, or would like to suggest a topic for the next episode, shoot us an email at podcast@padtinc.com we would love to hear from you!
The ANSYS finite element solvers enable a breadth and depth of capabilities unmatched by anyone in the world of computer-aided simulation. Thermal, Structural, Acoustic, Piezoelectric, Electrostatic and Circuit Coupled Electromagnetics are just an example of what can be simulated. Regardless of the type of simulation, each model is represented by a powerful scripting language, the ANSYS Parametric Design Language (APDL).
APDL is the foundation for all sophisticated features, many of which are not exposed in the Workbench Mechanical user interface. It also offers many conveniences such as parameterization, macros, branching and looping, and complex math operations. All these benefits are accessible within the ANSYS Mechanical APDL user interface.
Join PADT’s Principle & Co-Owner Eric Miller for a look at what’s new for MAPDL in ANSYS 2020 R1, regarding:
If this is your first time registering for one of our Bright Talk webinars, simply click the link and fill out the attached form. We promise that the information you provide will only be shared with those promoting the event (PADT).
You will only have to do this once! For all future webinars, you can simply click the link, add the reminder to your calendar and you’re good to go!
In this episode your host and Co-Founder of PADT, Eric Miller is joined by 3D Printing Applications Engineer Pamela Waterman and Advatech Pacific’s Engineering Manager Matt Humrick for a discussion on real world applications for topology optimization, and it’s value when it comes to creating parts though additive manufacturing.
If you would like to learn more about this topic and what Advatech Pacific is doing, you can download our case study covering these topics here: https://bit.ly/38Bqu2b
If you have any questions, comments, or would like to suggest a topic for the next episode, shoot us an email at podcast@padtinc.com we would love to hear from you!
