Making Sense of DC IR Results in Ansys SIwave

In this article I will cover a Voltage Drop (DC IR) simulation in SIwave, applying realistic power delivery setup on a simple 4-layer PCB design. The main goal for this project is to understand what data we receive by running DC IR simulation, how to verify it, and what is the best way of using it.

And before I open my tools and start diving deep into this topic, I would like to thank Zachary Donathan for asking the right questions and having deep meaningful technical discussions with me on some related subjects. He may not have known, but he was helping me to shape up this article in my head!

Design Setup

There are many different power nets present on the board under test, however I will be focusing on two widely spread nets +1.2V and +3.3V. Both nets are being supplied through Voltage Regulator Module (VRM), which will be assigned as a Voltage Source in our analysis. After careful assessment of the board design, I identified the most critical components for the power delivery to include in the analysis as Current Sources (also known as ‘sinks’). Two DRAM small outline integrated circuit (SOIC) components D1 and D2 are supplied with +1.2V. While power net +3.3V provides voltage to two quad flat package (QFP) microcontrollers U20 and U21, mini PCIE connector, and hex Schmitt-Trigger inverter U1.

Fig. 1. Power Delivery Network setting for a DC IR analysis

Figure 1 shows the ‘floor plan’ of the DC IR analysis setup with 1.2V voltage path highlighted in yellow and 3.3V path highlighted in light blue.

Before we assign any Voltage and Current sources, we need to define pin groups for all nets +1.2V, +3.3V and GND for all PDN component mentioned above. Having pin groups will significantly simplify the reviewing process of the results. Also, it is generally a good practice to start the DC IR analysis from the ‘big picture’ to understand if certain component gets enough power from the VRM. If a given IC reports an acceptable level of voltage being delivered with a good margin, then we don’t need to dig deeper; we can instead focus on those which may not have good enough margins.

Once we have created all necessary pin groups, we can assign voltage and current sources. There are several ways of doing that (using wizard or manual), for this project we will use ‘Generate Circuit Element on Components’ feature to manually define all sources. Knowing all the components and having pin groups already created makes the assignment very straight-forward. All current sources draw different amount of current, as indicated in our setting, however all current sources have the same Parasitic Resistance (very large value) and all voltage source also have the same Parasitic Resistance (very small value). This is shown on Figure 2 and Figure 3.

Note: The type of the current source ‘Constant Voltage’ or ‘Distributed Current’ matters only if you are assigning a current source to a component with multiple pins on the same net, and since in this project we are working with pins groups, this setting doesn’t make difference in final results.

Fig. 2. Voltage and Current sources assigned
Fig. 3. Parasitic Resistance assignments for all voltage and current sources

For each power net we have created a voltage source on VRM and multiple current sources on ICs and the connector. All sources have a negative node on a GND net, so we have a good common return path. And in addition, we have assigned a negative node of both voltage sources (one for +1.2V and one for +3.3V) as our reference points for our analysis. So reported voltage values will be referenced to that that node as absolute 0V.

At this point, the DC IR setup is complete and ready for simulation.

Results overview and validation

When the DC IR simulation is finished, there is large amount of data being generated, therefore there are different ways of viewing results, all options are presented on Figure 4. In this article I will be primarily focusing on ‘Power Tree’ and ‘Element Data’. As an additional source if validation we may review the currents and voltages overlaying the design to help us to visualize the current flow and power distribution. Most of the time this helps to understand if our assumption of pin grouping is accurate.

Fig. 4. Options to view different aspects of DC IR simulated data

Power Tree

First let’s look at the Power Tree, presented on Figure 5. Two different power nets were simulated, +1.2V and +3.3V, each of which has specified Current Sources where the power gets delivered. Therefore, when we analyze DC IR results in the Power tree format, we see two ‘trees’, one for each power net. Since we don’t have any pins, which would get both 1.2V and 3.3V at the same time (not very physical example), we don’t have ‘common branches’ on these two ‘trees’.

Now, let’s dissect all the information present in this power tree (taking in consideration only one ‘branch’ for simplicity, although the logic is applicable for all ‘branches’):

  • We were treating both power nets +1.2V and +3.3V as separate voltage loops, so we have assigned negative nodes of each Voltage Source as a reference point. Therefore, we see the ‘GND’ symbol ((1) and (2)) for each voltage source. Now all voltage calculations will be referenced to that node as 0V for its specific tree.
  • Then we see the path from Voltage Source to Current Source, the value ΔV shows the Voltage Drop in that path (3). Ultimately, this is the main value power engineers usually are interested in during this type of analysis. If we subtract ΔV from Vout we will get the ‘Actual Voltage’ delivered to the specific current source positive pin (1.2V – 0.22246V = 0.977V). That value reported in the box for the Current Source (4). Technically, the same voltage drop value is reported in the column ‘IR Drop’, but in this column we get more details – we see what the percentage of the Vout is being dropped. Engineers usually specify the margin value of the acceptable voltage drop as a percentage of Vout, and in our experiment we have specified 15%, as reported in column ‘Specification’. And we see that 18.5% is greater than 15%, therefore we get ‘Fail_I_&_V’ results (6) for that Current Source.
  • Regarding the current – we have manually specified the current value for each Current Source. Current values in Figure 2 are the same as in Figure 5. Also, we can specify the margin for the current to report pass or fail. In our example we assigned 108A as a current at the Current Source (5), while 100A is our current limit (4). Therefore, we also got failed results for the current as well.
  • As mentioned earlier, we assigned current values for each Current Source, but we didn’t set any current values for the Voltage Source. This is because the tool calculates how much current needs to be assigned for the Voltage Source, based on the value at the Current Sources. In our case we have 3 Current Sources 108A, 63A, 63A (5). The sum of these three values is 234A, which is reported as a current at the Voltage Source (7). Later we will see that this value is being used to calculate output power at the Voltage Source.  
Fig. 5. DC IR simulated data viewed as a ‘Power Tree’

Element Data

This option shows us results in the tabular representation. It lists many important calculated data points for specific objects, such as bondwire, current sources, all vias associated with the power distribution network, voltage probes, voltage sources.

Let’s continue reviewing the same power net +1.2V and the power distribution to CPU1 component as we have done for Power Tree (Figure 5). The same way we will be going over the details in point-by-point approach:

  • First and foremost, when we look at the information for Current Sources, we see a ‘Voltage’ value, which may be confusing. The value reported in this table is 0.7247V (8), which is different from the reported value of 0.977V in Power Tree on Figure 5 (4). The reason for the difference is that reported voltage value were calculated at different locations. As mentioned earlier, the reported voltage in the Power Tree is the voltage at the positive pin of the Current Source. The voltage reported in Element Data is the voltage at the negative pin of the Current Source, which doesn’t include the voltage drop across the ground plane of the return path.

To verify the reported voltage values, we can place Voltage Probes (under circuit elements). Once we do that, we will need to rerun the simulation in order to get the results for the probes:

  1. Two terminals of the ‘VPROBE_1’ attached at the positive pin of Voltage Source and at the positive pin of the Current Source. This probe should show us the voltage difference between VRM and IC, which also the same as reported Voltage Drop ΔV. And as we can see ‘VPROBE_1’ = 222.4637mV (13), when ΔV = 222.464mV (3). Correlated perfectly!
  2. Two terminals of the ‘VPROBE_GND’ attached to the negative pin of the Current Source and negative pin of the Voltage Source. The voltage shown by this probe is the voltage drop across the ground plane.

If we have 1.2V at the positive pin of VRM, then voltage drops 222.464mV across the power plane, so the positive pin of IC gets supplied with 0.977V. Then the voltage at the Current Source 0.724827V (8) being drawn, leaving us with (1.2V – 0.222464V – 0.724827V) = 0.252709V at the negative pin of the Current Source. On the return path the voltage drops again across the ground plane 252.4749mV (14) delivering back at the negative pin of VRM (0.252709V – 0.252475V) = 234uV. This is the internal voltage drop in the Voltage Source, as calculated as output current at VRM 234A (7) multiplied by Parasitic Resistance 1E-6Ohm (Figure 3) at VRM. This is Series R Voltage (11)

  • Parallel R Current of the Current source is calculated as Voltage 724.82mV (8) divided by Parasitic Resistance of the Current Source (Figure 3) 5E+7 Ohm = 1.44965E-8 (9)
  • Current of the Voltage Source report in the Element Data 234A (10) is the same value as reported in the Power Tree (sum of all currents of Current Sources for the +1.2V power net) = 234A (7). Knowing this value of the current we can multiple it by Parasitic Resistance of the Voltage Source (Figure 3) 1E-6 Ohm = (234A * 1E-6Ohm) = 234E-6V, which is equal to reported Series R Voltage (11). And considering that the 234A is the output current of the Voltage Source, we can multiple it by output voltage Vout = 1.2V to get a Power Output = (234A * 1.2V) = 280.85W (12)
Fig. 6. DC IR simulated data viewed in the table format as ‘Element Data’

In addition to all provided above calculations and explanations, the video below in Figure 7 highlights all the key points of this article.

Fig. 7. Difference between reporting Voltage values in Power Tree and Element Data

Conclusion

By carefully reviewing the Power Tree and Element Data reporting options, we can determine many important decisions about the power delivery network quality, such as how much voltage gets delivered to the Current Source; how much voltage drop is on the power net and on the ground net, etc. More valuable information can be extracted from other DC IR results options, such as ‘Loop Resistance’, ‘Path Resistance’, ‘RL table’, ‘Spice Netlist’, full ‘Report’. However, all these features deserve a separate topic.

As always, if you would like to receive more information related to this topic or have any questions please reach out to us at info@padtinc.com.

Bring Your Simulation Home with Ansys Cloud Solutions – Webinar

Engineering simulation has long been constrained by fixed computing resources available on a desktop or cluster. Today, however, cloud computing can deliver the on-demand, high performance computing (HPC) capacity required for faster high-fidelity results offering greater performance insight, all from the comfort of your home.

Ansys Cloud delivers the speed, power and compute capacity of cloud computing directly to your desktop — when and where you need it. You can run larger, more complex and more accurate simulations to gain more insight into your product — or you can evaluate more design variations to find the optimal design without long hardware/software procurement and deployment delays.

Join PADT’s Senior Application & Simulation Support Engineer Sina Ghods for a look at how Ansys is working to drive adoption by providing users a ready to use cloud service that provides:

  • Higher Fidelity Models
  • Faster Turnaround Time
  • Improved Productivity
  • Flexible Licensing
  • Multiple Supported Solvers
  • And Much More

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All Things Ansys 060: Tips For Making Working From Home More Productive

 

Published on: April 6th, 2020
With: Eric Miller & Matt Sutton
Description:  

In this episode your host and Co-Founder of PADT, Eric Miller is joined by PADT’s seasoned expert at working with Ansys from home Matt Sutton for a quick discussion on tips and best practices that make working from home more productive and effective.

If you would like to learn more about how PADT and Ansys can help you to better run your simulation from your home office, check out our webinar on the topic here: https://bit.ly/3dSa8WN

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Efficient and Accurate Simulation of Antenna Arrays in Ansys HFSS

Unit-cell in HFSS

HFSS offers different method of creating and simulating a large array. The explicit method, shown in Figure 1(a) might be the first method that comes to our mind. This is where you create the exact CAD of the array and solve it. While this is the most accurate method of simulating an array, it is computationally extensive. This method may be non-feasible for the initial design of a large array. The use of unit cell (Figure 1(b)) and array theory helps us to start with an estimate of the array performance by a few assumptions. Finite Array Domain Decomposition (or FADDM) takes advantage of unit cell simplicity and creates a full model using the meshing information generated in a unit cell. In this blog we will review the creation of unit cell. In the next blog we will explain how a unit cell can be used to simulate a large array and FADDM.

Fig. 1 (a) Explicit Array
Fig. 1 (b) Unit Cell
Fig. 1 (c) Finite Array Domain Decomposition (FADDM)

In a unit cell, the following assumptions are made:

  • The pattern of each element is identical.
  • The array is uniformly excited in amplitude, but not necessarily in phase.
  • Edge affects and mutual coupling are ignored
Fig. 2 An array consisting of elements amplitude and phases can be estimated with array theory, assuming all elements have the same amplitude and element radiation patterns. In unit cell simulation it is assumed all magnitudes (An’s) are equal (A) and the far field of each single element is equal.

A unit cell works based on Master/Slave (or Primary/Secondary) boundary around the cell. Master/Slave boundaries are always paired. In a rectangular cell you may use the new Lattice Pair boundary that is introduced in Ansys HFSS 2020R1. These boundaries are means of simulating an infinite array and estimating the performance of a relatively large arrays. The use of unit cell reduces the required RAM and solve time.

Primary/Secondary (Master/Slave) (or P/S) boundaries can be combined with Floquet port, radiation or PML boundary to be used in an infinite array or large array setting, as shown in Figure 3.

Fig. 3 Unit cell can be terminated with (a) radiation boundary, (b) Floquet port, (c) PML boundary, or combination of them.

To create a unit cell with P/S boundary, first start with a single element with the exact dimensions of the cell. The next step is creating a vacuum or airbox around the cell. For this step, set the padding in the location of P/S boundary to zero. For example, Figure 4 shows a microstrip patch antenna that we intend to create a 2D array based on this model. The array is placed on the XY plane. An air box is created around the unit cell with zero padding in X and Y directions.

Fig. 4 (a) A unit cell starts with a single element with the exact dimensions as it appears in the lattice
Fig. 4 (b) A vacuum box is added around it

You notice that in this example the vacuum box is larger than usual size of quarter wavelength that is usually used in creating a vacuum region around the antenna. We will get to calculation of this size in a bit, for now let’s just assign a value or parameter to it, as it will be determined later. The next step is to define P/S to generate the lattice. In AEDT 2020R1 this boundary is under “Coupled” boundary. There are two methods to create P/S: (1) Lattice Pair, (2) Primary/Secondary boundary.

Lattice Pair

The Lattice Pair works best for square lattices. It automatically assigns the primary and secondary boundaries. To assign a lattice pair boundary select the two sides that are supposed to create infinite periodic cells, right-click->Assign Boundary->Coupled->Lattice Pair, choose a name and enter the scan angles. Note that scan angles can be assigned as parameters. This feature that is introduced in 2020R1 does not require the user to define the UV directions, they are automatically assigned.

Fig. 5 The lattice pair assignment (a) select two lattice walls
Fig. 5 (b) Assign the lattice pair boundary
Fig. 5 (c) After, right-click and choosing assign boundary > choose Lattice Pair
Fig. 5 (d) Phi and Theta scan angles can be assigned as parameters

Primary/Secondary

Primary/Secondary boundary is the same as what used to be called Master/Slave boundary. In this case, each Secondary (Slave) boundary should be assigned following a Primary (Master) boundary UV directions. First choose the side of the cell that Primary boundary. Right-click->Assign Boundary->Coupled->Primary. In Primary Boundary window define U vector. Next select the secondary wall, right-click->Assign Boundary->Couple->Secondary, choose the Primary Boundary and define U vector exactly in the same direction as the Primary, add the scan angles (the same as Primary scan angles)

Fig. 6 Primary and secondary boundaries highlights.

Floquet Port and Modes Calculator

Floquet port excites and terminates waves propagating down the unit cell. They are similar to waveguide modes. Floquet port is always linked to P/S boundaries. Set of TE and TM modes travel inside the cell. However, keep in mind that the number of modes that are absorbed by the Floquet port are determined by the user. All the other modes are short-circuited back into the model. To assign a Floquet port two major steps should be taken:

Defining Floquet Port

Select the face of the cell that you like to assign the Floquet port. This is determined by the location of P/S boundary. The lattice vectors A and B directions are defined by the direction of lattice (Figure 7).

Fig. 7 Floquet port on top of the cell is defined based on UV direction of P/S pairs

The number of modes to be included are defined with the help of Modes Calculator. In the Mode Setup tab of the Floquet Port window, choose a high number of modes (e.g. 20) and click on Modes Calculator. The Mode Table Calculator will request your input of Frequency and Scan Angles. After selecting those, a table of modes and their attenuation using dB/length units are created. This is your guide in selecting the height of the unit cell and vaccume box. The attenation multiplied by the height of the unit cell (in the project units, defined in Modeler->Units) should be large enough to make sure the modes are attenuated enough so removing them from the calcuatlion does not cause errors. If the unit cell is too short, then you will see many modes are not attenuated enough. The product of the attenuatin and height of the airbox should be at least 50 dB. After the correct size for the airbox is calcualted and entered, the model with high attenuation can be removed from the Floquet port definition.

The 3D Refinement tab is used to control the inclusion of the modes in the 3D refinement of the mesh. It is recommended not to select them for the antenna arrays.

Fig. 8 (Left) Determining the scan angles for the unit cell, (Right) Modes Calculator showing the Attenuation

In our example, Figure 8 shows that the 5th mode has an attenuation of 2.59dB/length. The height of the airbox is around 19.5mm, providing 19.5mm*2.59dB/mm=50.505dB attenuation for the 5th mode. Therefore, only the first 4 modes are kept for the calculations. If the height of the airbox was less than 19.5mm, we would need to increase the height so accordingly for an attenuation of at least 50dB.

Radiation Boundary

A simpler alternative for Floquet port is radiation boundary. It is important to note that the size of the airbox should still be kept around the same size that was calculated for the Floquet port, therefore, higher order modes sufficiently attenuated. In this case the traditional quarter wavelength padding might not be adequate.

Fig. 9 Radiation boundary on top of the unit cell

Perfectly Matched Layer

Although using radiation boundary is much simpler than Floquet port, it is not accurate for large scan angles. It can be a good alternative to Floquet port only if the beam scanning is limited to small angles. Another alternative to Floquet port is to cover the cell by a layer of PML. This is a good compromise and provides very similar results to Floquet port models. However, the P/S boundary need to surround the PML layer as well, which means a few additional steps are required. Here is how you can do it:

  1. Reduce the size of the airbox* slightly, so after adding the PML layer, the unit cell height is the same as the one that was generated using the Modes Calculation. (For example, in our model airbox height was 19mm+substrte thickness, the PML height was 3mm, so we reduced the airbox height to 16mm).
  2. Choose the top face and add PML boundary.
  3. Select each side of the airbox and create an object from that face (Figure 10).
  4. Select each side of the PML and create objects from those faces (Figure 10).
  5. Select the two faces that are on the same plane from the faces created from airbox and PML and unite them to create a side wall (Figure 10).
  6. Then assign P/S boundary to each pair of walls (Figure 10).

*Please note for this method, an auto-size “region” cannot be used, instead draw a box for air/vacuum box. The region does not let you create the faces you need to combine with PML faces.

Fig. 10 Selecting two faces created from airbox and PML and uniting them to assign P/S boundaries

The advantage of PML termination over Floquet port is that it is simpler and sometimes faster calculation. The advantage over Radiation Boundary termination is that it provides accurate results for large scan angles. For better accuracy the mesh for the PML region can be defined as length based.

Seed the Mesh

To improve the accuracy of the PML model further, an option is to use length-based mesh. To do this select the PML box, from the project tree in Project Manager window right-click on Mesh->Assign Mesh Operation->On Selection->Length Based. Select a length smaller than lambda/10.

Fig. 11 Using element length-based mesh refinement can improve the accuracy of PML design

Scanning the Angle

In phased array simulation, we are mostly interested in the performance of the unit cell and array at different scan angles. To add the scanning option, the phase of P/S boundary should be defined by project or design parameters. The parameters can be used to run a parametric sweep, like the one shown in Figure 12. In this example the theta angle is scanned from 0 to 60 degrees.

Fig. 12 Using a parametric sweep, the scanned patterns can be generated

Comparing PML and Floquet Port with Radiation Boundary

To see the accuracy of the radiation boundary vs. PML and Floquet Port, I ran the simulations for scan angles up to 60 degrees for a single element patch antenna. Figure 13 shows that the accuracy of the Radiation boundary drops after around 15 degrees scanning. However, PML and Floquet port show similar performance.

Fig. 13 Comparison of radiation patterns using PML (red), Floquet Port (blue), and Radiation boundary (orange).

S Parameters

To compare the accuracy, we can also check the S parameters. Figure 14 shows the comparison of active S at port 1 for PML and Floquet port models. Active S parameters were used since the unit cell antenna has two ports. Figure 15 shows how S parameters compare for the model with the radiation boundary and the one with the Floquet port.

Fig. 14 Active S parameter comparison for different scan angles, PML vs. Floquet Port model.
Fig. 15 Active S parameter comparison for different scan angles, Radiation Boundary vs. Floquet Port model.

Conclusion

The unit cell definition and options on terminating the cell were discussed here. Stay tuned. In the next blog we discuss how the unit cell is utilized in modeling antenna arrays.

Test, Design & Analyze From Home With Ansys Simulation Software – Webinar

As companies are closing their doors in order to help ensure the health and safety of their employees and customers, those that can are pivoting to working form home.

But what about those working on product design, testing, and analysis that require a physical presence?

Here at PADT we know that the show must go on, and companies working across various technical professions are needed to keep the world moving forward, especially in these trying times. Thus we would like to introduce a solution: Ansys Engineering Simulation Software.

Join The PADT team for a panel discussion on how you can use simulation to move your in-person workflow to a digital environment, as well as what specific Ansys tools can be used to access your work from home.

All of this will be followed by a live Q&A in which our expert staff will take any questions regarding your specific concerns with transitioning your workflow and all other things related to working from home.

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All Things Ansys 059: Elements, Contact & Solver Updates in Ansys MAPDL 2020 R1

 

Published on: March 23rd, 2020
With: Eric Miller, Ted Harris, Alex Grishin & Joe Woodward
Description:  

In this episode your host and Co-Founder of PADT, Eric Miller is joined by PADT’s Ted Harris, Alex Grishin, and Joe Woodward to discuss their favorite features in the MAPDL Updates in Ansys 2020 R1.

If you would like to learn more about this topic, you can view PADT’s webinar covering these updates here: https://bit.ly/2WD88vt

Additionally, if you would like to take part in the survey mentioned at the start of the episode click the link here: https://bit.ly/3biWkCp

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MAPDL – Elements, Contact & Solver Updates in Ansys 2020 R1 – Webinar

The ANSYS finite element solvers enable a breadth and depth of capabilities unmatched by anyone in the world of computer-aided simulation. Thermal, Structural, Acoustic, Piezoelectric, Electrostatic and Circuit Coupled Electromagnetics are just an example of what can be simulated. Regardless of the type of simulation, each model is represented by a powerful scripting language, the ANSYS Parametric Design Language (APDL).

APDL is the foundation for all sophisticated features, many of which are not exposed in the Workbench Mechanical user interface. It also offers many conveniences such as parameterization, macros, branching and looping, and complex math operations. All these benefits are accessible within the ANSYS Mechanical APDL user interface.

Join PADT’s Principle & Co-Owner Eric Miller for a look at what’s new for MAPDL in ANSYS 2020 R1, regarding:

  • Linear Dynamics
  • Elements
  • Contacts
  • Post Processing
  • Solver Components
  • And Much More

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All Things Ansys 058: Combining Mechanical Simulation with Additive Manufacturing

 

Published on: March 9th, 2020
With: Eric Miller, Matt Humrick & Pam Waterman
Description:  

In this episode your host and Co-Founder of PADT, Eric Miller is joined by 3D Printing Applications Engineer Pamela Waterman and Advatech Pacific’s Engineering Manager Matt Humrick for a discussion on real world applications for topology optimization, and it’s value when it comes to creating parts though additive manufacturing.

If you would like to learn more about this topic and what Advatech Pacific is doing, you can download our case study covering these topics here: https://bit.ly/38Bqu2b

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All Things ANSYS 057: Simulation for Additive Manufacturing in ANSYS 2020 R1

 

Published on: February 24th, 2020
With: Eric Miller & Doug Oatis
Description:  

In this episode your host and Co-Founder of PADT, Eric Miller is joined by Lead Mechanical Engineer Doug Oatis for a discussion on the latest advancements in simulation for additive manufacturing and topology optimization in ANSYS 2020 R1.

If you would like to learn more about what this release is capable of, check out our webinar on the topic here:

https://www.brighttalk.com/webcast/15747/384528

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Additive Manufacturing & Topology Optimization in ANSYS 2020 R1 – Webinar

ANSYS offers a complete simulation workflow for additive manufacturing (AM) that allows you to transition your R&D efforts for metal additive manufacturing into a successful manufacturing operation. This best-in-class solution for additive manufacturing enables simulation at every step in your AM process. It will help you optimize material configurations and machine and parts setup before you begin to print. As a result, you’ll greatly reduce — and potentially eliminate — the physical process of trial-and- error testing.

ANSYS additive solutions continue to evolve at a rapid pace. A variety of new enhancements and features come as part of ANSYS 2020 R1, including the ability to work with EOS printers, using the inherent strain approach in ANSYS Workbench Additive, and new materials in ANSYS Additive Print and Science.

Join PADT’s Lead Mechanical Engineer Doug Oatis for an exploration of the ANSYS tools that help to optimize additive manufacturing, and what new capabilities are available for them when upgrading to ANSYS 2020 R1. This presentation includes updates regarding:

  • Level-set topology optimization
  • Density based topology optimization
  • Inherent strain method in workbench Additive
  • Improved supports in Additive Prep
  • Additive Wizard update
  • And much more

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All Things ANSYS 055: Introducing ANSYS 2020

 

Published on: February 3rd, 2020
With: Eric Miller, Josh Stout, Sina Gohds, Ted Harris & Tom Chadwick
Description:  

In this episode your host and Co-Founder of PADT, Eric Miller is joined by Josh Stout, Sina Gohds, Ted Harris, and Tom Chadwick from the simulation support team to discuss their thoughts on ANSYS 2020 R1, and what specific capabilities they are excited about exploring after attending the annual ANSYS sales kickoff in Florida.

This new release covers updates for the entirety of the ANSYS suite of tools, so there is a lot to talk about.

If you have any questions, comments, or would like to suggest a topic for the next episode, shoot us an email at podcast@padtinc.com we would love to hear from you!

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Fluent Updates in ANSYS 2020 R1 – Webinar

Computational fluid dynamics (CFD) can be challenging for a multitude of reasons, but not with ANSYS Fluent. Anyone can get great CFD simulation results with ANSYS solutions. Fluent software contains the broad, physical modeling capabilities needed to model flow, turbulence, heat transfer and reactions for industrial applications. These range from air flow over an aircraft wing to combustion in a furnace, from bubble columns to oil platforms, from blood flow to semiconductor manufacturing and from clean room design to wastewater treatment plants.

Fluent spans an expansive range, including special models, with capabilities to model in-cylinder combustion, aero-acoustics, turbomachinery and multiphase systems. The latest innovations and updates simplify and speed setup and meshing while adding even more accurate physical models. The outcome: great results, without compromise.

Join PADT’s Senior CFD & FEA Application Engineer, Sina Ghods, for a look at what’s new and improved in this latest version of ANSYS Fluent, including:

  • User Interface/Graphics
  • Meshing Workflows
  • Multi-phase Robustness
  • Solver Enhancements
  • And much more

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Mechanical Updates in ANSYS 2020 R1 – Webinar

With ANSYS structural analysis software, users are able to solve more complex engineering problems, faster and more efficiently than ever before. Customization and automation of structural solutions is much easier to optimize thanks to new and innovative finite element analysis (FEA) tools available in this product suite.

Once again, ANSYS is able to cement their role as industry leaders when it comes to usability, productivity, and reliability; adding innovative functionality to an already groundbreaking product offering. ANSYS Mechanical continues to be used throughout the industry, and for good reason as it enables engineers to optimize their product design and reduce the costs of physical testing.

Join PADT’s Senior Mechanical Engineer & Lead Trainer Joe Woodward, for an in-depth look at what’s new in the latest version of ANSYS Mechanical, including updates regarding:

  • External Modeling
  • Graphics
  • Composites
  • Linear Dynamics
  • And much more

Register Here

If this is your first time registering for one of our Bright Talk webinars, simply click the link and fill out the attached form. We promise that the information you provide will only be shared with those promoting the event (PADT).

You will only have to do this once! For all future webinars, you can simply click the link, add the reminder to your calendar and you’re good to go!

Reduce EMI with Good Signal Integrity Habits

Recently the ‘Signal Integrity Journal’ posted their ‘Top 10 Articles’ of 2019. All of the articles included were incredible, however, one stood out to me from the rest – ‘Seven Habits of Successful 2-Layer Board Designers’ by Dr. Eric Bogatin (https://www.signalintegrityjournal.com/blogs/12-fundamentals/post/1207-seven-habits-of-successful-2-layer-board-designers). In this work, Dr. Bogatin and his students were developing a 2-Layer printed circuit board (PCB), while trying to minimize signal and power Integrity issues as much as possible. As a result, they developed a board and described seven ‘golden habits’ for this board development. These are fantastic habits that I’m confident we can all agree with. In particular, there was one habit at which I wanted to take a deeper look:

“…Habit 4: When you need to route a cross-under on the bottom layer, make it short. When you can’t make it short, add a return strap over it..”

Generally speaking, this habit suggests to be very careful with the routing of signal traces over the gap on the ground plane. From the signal integrity point of view, Dr. Bogatin explained it perfectly – “..The signal traces routed above this gap will see a gap in the return path and generate cross talk to other signals also crossing the gap..”. On one hand, crosstalk won’t be a problem if there are no other nets around, so the layout might work just fine in that case. However, crosstalk is not the only risk. Fundamentally, crosstalk is an EMI problem. So, I wanted to explore what happens when this habit is ignored and there are no nearby nets to worry about.

To investigate, I created a simple 2-Layer board with the signal trace, connected to 5V voltage source, going over an air gap. Then I observed the near field and far field results using ANSYS SIwave solution. Here is what I found.

Near and Far Field Analysis

Typically, near and far fields are characterized by solved E and H fields around the model. This feature in ANSYS SIwave gives the engineer the ability to simulate both E and H fields for near field analysis, and E field for Far Field analysis.

First and foremost, we can see, as expected, that both near and far Field have resonances at the same frequencies. Additionally, we can observe from Figure 1 that both E and H fields for near field have the largest radiation spikes at 786.3 MHz and 2.349GHz resonant frequencies.

Figure 1. Plotted E and H fields for both Near and Far Field solutions

If we plot E and H fields for Near Field, we can see at which physical locations we have the maximum radiation.

Figure 2. Plotted E and H fields for Near field simulations

As expected, we see the maximum radiation occurring over the air gap, where there is no return path for the current. Since we know that current is directly related to electromagnetic fields, we can also compute AC current to better understand the flow of the current over the air gap.

Compute AC Currents (PSI)

This feature has a very simple setup interface. The user only needs to make sure that the excitation sources are read correctly and that the frequency range is properly indicated. A few minutes after setting up the simulation, we get frequency dependent results for current. We can review the current flow at any simulated frequency point or view the current flow dynamically by animating the plot.

Figure 3. Computed AC currents

As seen in Figure 3, we observe the current being transferred from the energy source, along the transmission line to the open end of the trace. On the ground layer, we see the return current directed back to the source. However at the location of the air gap there is no metal for the return current to flow, therefore, we can see the unwanted concentration of energy along the plane edges. This energy may cause electromagnetic radiation and potential problems with emission.

If we have a very complicated multi-layer board design, it won’t be easy to simulate current flow on near and far fields for the whole board. It is possible, but the engineer will have to have either extra computing time or extra computing power. To address this issue, SIwave has a feature called EMI Scanner, which helps identify problematic areas on the board without running full simulations.

EMI Scanner

ANSYS EMI Scanner, which is based on geometric rule checks, identifies design issues that might result in electromagnetic interference problems during operation. So, I ran the EMI Scanner to quickly identify areas on the board which may create unwanted EMI effects. It is recommended for engineers, after finding all potentially problematic areas on the board using EMI Scanner, to run more detailed analyses on those areas using other SIwave features or HFSS.

Currently the EMI Scanner contains 17 rules, which are categorized as ‘Signal Reference’, ‘Wiring/Crosstalk’, ‘Decoupling’ and ‘Placement’. For this project, I focused on the ‘Signal Reference’ rules group, to find violations for ‘Net Crossing Split’ and ‘Net Near Edge of Reference’. I will discuss other EMI Scanner rules in more detail in a future blog (so be sure to check back for updates).

Figure 4. Selected rules in EMI Scanner (left) and predicted violations in the project (right)

As expected, the EMI Scanner properly identified 3 violations as highlighted in Figure 4. You can either review or export the report, or we can analyze violations with iQ-Harmony. With this feature, besides generating a user-friendly report with graphical explanations, we are also able to run ‘What-if’ scenarios to see possible results of the geometrical optimization.

Figure 5. Generated report in iQ-Harmony with ‘What-If’ scenario

Based on these results of quick EMI Scanner, the engineer would need to either redesign the board right away or to run more analysis using a more accurate approach.

Conclusion

In this blog, we were able to successfully run simulations using ANSYS SIwave solution to understand the effect of not following Dr.Bogatin’s advice on routing the signal trace over the gap on a 2-Layer board. We also were able to use 4 different features in SIwave, each of which delivered the correct, expected results.

Overall, it is not easy to think about all possible SI/PI/EMI issues while developing a complex board. In these modern times, engineers don’t need to manufacture a physical board to evaluate EMI problems. A lot of developmental steps can now be performed during simulations, and ANSYS SIwave tool in conjunction with HFSS Solver can help to deliver the right design on the first try.

If you would like more information or have any questions please reach out to us at info@padtinc.com.

All Thing ANSYS 054: Talking CFD – Discussion on the Current State of Computational Fluid Dynamics with Robin Knowles

 

Published on: January 13th, 2020
With: Eric Miller & Robin Knowles
Description:  

In this episode we are excited to share an interview done with host and Co-Founder of PADT, Eric Miller and host of the Talking CFD podcast Robin Knowles, regarding the history of PADT’s use of simulation technology as a whole, and the current state of all things CFD.

If you would like to hear more of Robin’s interviews with various other CFD based companies both small and large, you can listen at https://www.cfdengine.com/podcast/.

If you have any questions, comments, or would like to suggest a topic for the next episode, shoot us an email at podcast@padtinc.com we would love to hear from you!

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