Windows Update KB4571756 Triggers Error 3221227010 for Ansys Electronics Products

On September 7, 2020 Microsoft released a Windows update KB4571756, which may cause the Ansys electronic products to fail with the Error:

3221227010 at ‘reg_ansysedt.exe’ and ‘reg_siwave.exe’ registration.

This is the error message, users would see if they right-mouse-click and run the following file as administrator:

C:\Program Files\AnsysEM\AnsysEM20.2\Win64\config\ConfigureThisMachine.exe

To resolve this issue, here are the steps we recommend users take:

  1. Revert the updates.
    1. If the issue is not resolved or something your IT won’t let you do, continue to the next steps.
  2. Set an environment variable that turns off the driver that is causing the error. 
    1. Use windows search and type “system environment” and click on “Edit the system environment variables”
    2. This opens the “System Properties” tool
    3. Go to the “Advanced” tab
    4. Click on “Environment Variables…” at the bottom
    5. In the System Variables window click on “New…”
    6. Create the following variable:

      Variable Name: ANSYS_EM_DONOT_PRELOAD_3DDRIVER_DLL
      Variable Value: 1
    7. Click OK 3 times to exit out of the tool and save your changes. 
  3. If the issue is still not resolved, there is one more step:
    1. Go to C:\Program Files\AnsysEM\AnsysEM20.2\Win64\config\
    2. Right-Mouse-Click on “ConfigureThisMachine.exe” and run as Admin. 

If these steps helped to resolve the issue, you will see the following info message when ‘ConfigureThisMachine.exe’ is run:

If this does not work, please contact your Ansys support provider. 

Reduce EMI with Good Signal Integrity Habits

Recently the ‘Signal Integrity Journal’ posted their ‘Top 10 Articles’ of 2019. All of the articles included were incredible, however, one stood out to me from the rest – ‘Seven Habits of Successful 2-Layer Board Designers’ by Dr. Eric Bogatin (https://www.signalintegrityjournal.com/blogs/12-fundamentals/post/1207-seven-habits-of-successful-2-layer-board-designers). In this work, Dr. Bogatin and his students were developing a 2-Layer printed circuit board (PCB), while trying to minimize signal and power Integrity issues as much as possible. As a result, they developed a board and described seven ‘golden habits’ for this board development. These are fantastic habits that I’m confident we can all agree with. In particular, there was one habit at which I wanted to take a deeper look:

“…Habit 4: When you need to route a cross-under on the bottom layer, make it short. When you can’t make it short, add a return strap over it..”

Generally speaking, this habit suggests to be very careful with the routing of signal traces over the gap on the ground plane. From the signal integrity point of view, Dr. Bogatin explained it perfectly – “..The signal traces routed above this gap will see a gap in the return path and generate cross talk to other signals also crossing the gap..”. On one hand, crosstalk won’t be a problem if there are no other nets around, so the layout might work just fine in that case. However, crosstalk is not the only risk. Fundamentally, crosstalk is an EMI problem. So, I wanted to explore what happens when this habit is ignored and there are no nearby nets to worry about.

To investigate, I created a simple 2-Layer board with the signal trace, connected to 5V voltage source, going over an air gap. Then I observed the near field and far field results using ANSYS SIwave solution. Here is what I found.

Near and Far Field Analysis

Typically, near and far fields are characterized by solved E and H fields around the model. This feature in ANSYS SIwave gives the engineer the ability to simulate both E and H fields for near field analysis, and E field for Far Field analysis.

First and foremost, we can see, as expected, that both near and far Field have resonances at the same frequencies. Additionally, we can observe from Figure 1 that both E and H fields for near field have the largest radiation spikes at 786.3 MHz and 2.349GHz resonant frequencies.

Figure 1. Plotted E and H fields for both Near and Far Field solutions

If we plot E and H fields for Near Field, we can see at which physical locations we have the maximum radiation.

Figure 2. Plotted E and H fields for Near field simulations

As expected, we see the maximum radiation occurring over the air gap, where there is no return path for the current. Since we know that current is directly related to electromagnetic fields, we can also compute AC current to better understand the flow of the current over the air gap.

Compute AC Currents (PSI)

This feature has a very simple setup interface. The user only needs to make sure that the excitation sources are read correctly and that the frequency range is properly indicated. A few minutes after setting up the simulation, we get frequency dependent results for current. We can review the current flow at any simulated frequency point or view the current flow dynamically by animating the plot.

Figure 3. Computed AC currents

As seen in Figure 3, we observe the current being transferred from the energy source, along the transmission line to the open end of the trace. On the ground layer, we see the return current directed back to the source. However at the location of the air gap there is no metal for the return current to flow, therefore, we can see the unwanted concentration of energy along the plane edges. This energy may cause electromagnetic radiation and potential problems with emission.

If we have a very complicated multi-layer board design, it won’t be easy to simulate current flow on near and far fields for the whole board. It is possible, but the engineer will have to have either extra computing time or extra computing power. To address this issue, SIwave has a feature called EMI Scanner, which helps identify problematic areas on the board without running full simulations.

EMI Scanner

ANSYS EMI Scanner, which is based on geometric rule checks, identifies design issues that might result in electromagnetic interference problems during operation. So, I ran the EMI Scanner to quickly identify areas on the board which may create unwanted EMI effects. It is recommended for engineers, after finding all potentially problematic areas on the board using EMI Scanner, to run more detailed analyses on those areas using other SIwave features or HFSS.

Currently the EMI Scanner contains 17 rules, which are categorized as ‘Signal Reference’, ‘Wiring/Crosstalk’, ‘Decoupling’ and ‘Placement’. For this project, I focused on the ‘Signal Reference’ rules group, to find violations for ‘Net Crossing Split’ and ‘Net Near Edge of Reference’. I will discuss other EMI Scanner rules in more detail in a future blog (so be sure to check back for updates).

Figure 4. Selected rules in EMI Scanner (left) and predicted violations in the project (right)

As expected, the EMI Scanner properly identified 3 violations as highlighted in Figure 4. You can either review or export the report, or we can analyze violations with iQ-Harmony. With this feature, besides generating a user-friendly report with graphical explanations, we are also able to run ‘What-if’ scenarios to see possible results of the geometrical optimization.

Figure 5. Generated report in iQ-Harmony with ‘What-If’ scenario

Based on these results of quick EMI Scanner, the engineer would need to either redesign the board right away or to run more analysis using a more accurate approach.

Conclusion

In this blog, we were able to successfully run simulations using ANSYS SIwave solution to understand the effect of not following Dr.Bogatin’s advice on routing the signal trace over the gap on a 2-Layer board. We also were able to use 4 different features in SIwave, each of which delivered the correct, expected results.

Overall, it is not easy to think about all possible SI/PI/EMI issues while developing a complex board. In these modern times, engineers don’t need to manufacture a physical board to evaluate EMI problems. A lot of developmental steps can now be performed during simulations, and ANSYS SIwave tool in conjunction with HFSS Solver can help to deliver the right design on the first try.

If you would like more information or have any questions please reach out to us at info@padtinc.com.

ANSYS 17.2 Executable Paths on Linux


ansys-linux-penguin-1When running on a machine with a Linux operating system, it is not uncommon for users to want to run from the command line or with a shell script. To do this you need to know where the actual executable files are located. Based on a request from a customer, we have tried to coalesce the major ANSYS product executables that can be run via command line on Linux into a single list:

ANSYS Workbench (Includes ANSYS Mechanical, Fluent, CFX, Polyflow, Icepak, Autodyn, Composite PrepPost, DesignXplorer, DesignModeler, etc.):

/ansys_inc/v172/Framework/bin/Linux64/runwb2

ANSYS Mechanical APDL, a.k.a. ANSYS ‘classic’:

/ansys_inc/v172/ansys/bin/launcher172 (brings up the MAPDL launcher menu)
/ansys_inc/v172/ansys/bin/mapdl (launches ANSYS MAPDL)

CFX Standalone:

/ansys_inc/v172/CFX/bin/cfx5

Autodyn Standalone:

/ansys_inc/v172/autodyn/bin/autodyn172

Note: A required argument for Autodyn is –I {ident-name}

Fluent Standalone (Fluent Launcher):

/ansys_inc/v172/fluent/bin/fluent

Icepak Standalone:

/ansys_inc/v172/Icepak/bin/icepak

Polyflow Standalone:

/ansys_inc/v172/polyflow/bin/polyflow/polyflow < my.dat

Chemkin:

/ansys_inc/v172/reaction/chemkinpro.linuxx8664/bin/chemkinpro_setup.ksh

Forte:

/ansys_inc/v172/reaction/forte.linuxx8664/bin/forte.sh

TGRID:

/ansys_inc/v172/tgrid/bin/tgrid

ANSYS Electronics Desktop (for Ansoft tools, e.g. Maxwell, HFSS)

/ansys_inc/v172/AnsysEM/AnsysEM17.2/Linux64/ansysedt

SIWave:

/ansys_inc/v172/AnsysEM/AnsysEM17.2/Linux64/siwave

An Eye for the Win! – Signal Integrity with ANSYS

DDRComparisonIn today’s world of high speed communication we are continuously pushing the envelope in data throughput and reliability – There are many challenges that restrict speedy progress: Time – Spinning multiple boards to find and fix problems costs valuable time and money; Cost – additional test procedures can significantly add to this cost; Scalability of Solutions – it’s fundamentally difficult to accurately predict what might happen solely through previous experiences; which is often why multiple spins are required.

ANSYS has the simulation platform that enable signal integrity engineers to predict and improve the performance of high speed communication channels before any board is prototyped – Imagine being able get the design right the first time by testing several design parameters such as different trace routing, power profiles and components.

This sounds like a great proposition but in actuality what do you get from doing that? The answer is a reduced design cost, detailed insight into the design and a reduced time to market. The only way to obtain this “full picture” is to understand the electrical, thermal and mechanical aspects of the design.

EyediagramEye Diagram of Data Signal Obtained in ANSYS

A critical characterization in high speed communication channel design is the Eye diagram. Extensive testing is done to obtain Eye diagrams for various signal nets across a PCB or Package – ANSYS can provide the Eye diagram so that engineers can address potential failures and weaknesses in their design before it is sent out for prototyping. Bathtub curves, effects of jitter and identifying crosstalk are equally important in the design of communication channels and all can be obtained and considered with ANSYS tools.

ANSYS supports IBIS-AMI modeling, SERDES design, TDR measurement and Statistical Eye analysis among much more. With chip, memory and board manufacturers all utilizing ANSYS products it is easy to incorporate and analyze real world product performance of the entire PCB.

TDRTDR Measurement Across Net

ANSYS allows all aspects of the design to be tested and optimized before prototyping. Apart from signal integrity ANSYS tools can also accurately model power integrity concerns such as decoupling capacitor optimization, thermal response and structural issues, as well as cooling solutions for chips, packages, PCBs and full electronic systems. With the ability to analyze and help optimize different design characteristics of a PCB, ANSYS can provide engineers with “the full picture” to help reduce cost and time to market, and to understand the design’s expected real world operation.

VoltageDropBoardWarpageElectronicsCooling

Top: Voltage Drop; Middle: PCB Warpage;
Bottom: Cooling Flow Through Enclosure

The “Eye” is only a phone call away.

Please give us a call at 1-800-293-PADT or reach out to me directly at manoj@padtinc.com for more information.

Getting to know ANSYS – SIwave

This video is an introduction to ANSYS SIwave – an analysis tool for Integrated Circuits and PCBs