Making Sense of DC IR Results in Ansys SIwave

In this article I will cover a Voltage Drop (DC IR) simulation in SIwave, applying realistic power delivery setup on a simple 4-layer PCB design. The main goal for this project is to understand what data we receive by running DC IR simulation, how to verify it, and what is the best way of using it.

And before I open my tools and start diving deep into this topic, I would like to thank Zachary Donathan for asking the right questions and having deep meaningful technical discussions with me on some related subjects. He may not have known, but he was helping me to shape up this article in my head!

Design Setup

There are many different power nets present on the board under test, however I will be focusing on two widely spread nets +1.2V and +3.3V. Both nets are being supplied through Voltage Regulator Module (VRM), which will be assigned as a Voltage Source in our analysis. After careful assessment of the board design, I identified the most critical components for the power delivery to include in the analysis as Current Sources (also known as ‘sinks’). Two DRAM small outline integrated circuit (SOIC) components D1 and D2 are supplied with +1.2V. While power net +3.3V provides voltage to two quad flat package (QFP) microcontrollers U20 and U21, mini PCIE connector, and hex Schmitt-Trigger inverter U1.

Fig. 1. Power Delivery Network setting for a DC IR analysis

Figure 1 shows the ‘floor plan’ of the DC IR analysis setup with 1.2V voltage path highlighted in yellow and 3.3V path highlighted in light blue.

Before we assign any Voltage and Current sources, we need to define pin groups for all nets +1.2V, +3.3V and GND for all PDN component mentioned above. Having pin groups will significantly simplify the reviewing process of the results. Also, it is generally a good practice to start the DC IR analysis from the ‘big picture’ to understand if certain component gets enough power from the VRM. If a given IC reports an acceptable level of voltage being delivered with a good margin, then we don’t need to dig deeper; we can instead focus on those which may not have good enough margins.

Once we have created all necessary pin groups, we can assign voltage and current sources. There are several ways of doing that (using wizard or manual), for this project we will use ‘Generate Circuit Element on Components’ feature to manually define all sources. Knowing all the components and having pin groups already created makes the assignment very straight-forward. All current sources draw different amount of current, as indicated in our setting, however all current sources have the same Parasitic Resistance (very large value) and all voltage source also have the same Parasitic Resistance (very small value). This is shown on Figure 2 and Figure 3.

Note: The type of the current source ‘Constant Voltage’ or ‘Distributed Current’ matters only if you are assigning a current source to a component with multiple pins on the same net, and since in this project we are working with pins groups, this setting doesn’t make difference in final results.

Fig. 2. Voltage and Current sources assigned
Fig. 3. Parasitic Resistance assignments for all voltage and current sources

For each power net we have created a voltage source on VRM and multiple current sources on ICs and the connector. All sources have a negative node on a GND net, so we have a good common return path. And in addition, we have assigned a negative node of both voltage sources (one for +1.2V and one for +3.3V) as our reference points for our analysis. So reported voltage values will be referenced to that that node as absolute 0V.

At this point, the DC IR setup is complete and ready for simulation.

Results overview and validation

When the DC IR simulation is finished, there is large amount of data being generated, therefore there are different ways of viewing results, all options are presented on Figure 4. In this article I will be primarily focusing on ‘Power Tree’ and ‘Element Data’. As an additional source if validation we may review the currents and voltages overlaying the design to help us to visualize the current flow and power distribution. Most of the time this helps to understand if our assumption of pin grouping is accurate.

Fig. 4. Options to view different aspects of DC IR simulated data

Power Tree

First let’s look at the Power Tree, presented on Figure 5. Two different power nets were simulated, +1.2V and +3.3V, each of which has specified Current Sources where the power gets delivered. Therefore, when we analyze DC IR results in the Power tree format, we see two ‘trees’, one for each power net. Since we don’t have any pins, which would get both 1.2V and 3.3V at the same time (not very physical example), we don’t have ‘common branches’ on these two ‘trees’.

Now, let’s dissect all the information present in this power tree (taking in consideration only one ‘branch’ for simplicity, although the logic is applicable for all ‘branches’):

  • We were treating both power nets +1.2V and +3.3V as separate voltage loops, so we have assigned negative nodes of each Voltage Source as a reference point. Therefore, we see the ‘GND’ symbol ((1) and (2)) for each voltage source. Now all voltage calculations will be referenced to that node as 0V for its specific tree.
  • Then we see the path from Voltage Source to Current Source, the value ΔV shows the Voltage Drop in that path (3). Ultimately, this is the main value power engineers usually are interested in during this type of analysis. If we subtract ΔV from Vout we will get the ‘Actual Voltage’ delivered to the specific current source positive pin (1.2V – 0.22246V = 0.977V). That value reported in the box for the Current Source (4). Technically, the same voltage drop value is reported in the column ‘IR Drop’, but in this column we get more details – we see what the percentage of the Vout is being dropped. Engineers usually specify the margin value of the acceptable voltage drop as a percentage of Vout, and in our experiment we have specified 15%, as reported in column ‘Specification’. And we see that 18.5% is greater than 15%, therefore we get ‘Fail_I_&_V’ results (6) for that Current Source.
  • Regarding the current – we have manually specified the current value for each Current Source. Current values in Figure 2 are the same as in Figure 5. Also, we can specify the margin for the current to report pass or fail. In our example we assigned 108A as a current at the Current Source (5), while 100A is our current limit (4). Therefore, we also got failed results for the current as well.
  • As mentioned earlier, we assigned current values for each Current Source, but we didn’t set any current values for the Voltage Source. This is because the tool calculates how much current needs to be assigned for the Voltage Source, based on the value at the Current Sources. In our case we have 3 Current Sources 108A, 63A, 63A (5). The sum of these three values is 234A, which is reported as a current at the Voltage Source (7). Later we will see that this value is being used to calculate output power at the Voltage Source.  
Fig. 5. DC IR simulated data viewed as a ‘Power Tree’

Element Data

This option shows us results in the tabular representation. It lists many important calculated data points for specific objects, such as bondwire, current sources, all vias associated with the power distribution network, voltage probes, voltage sources.

Let’s continue reviewing the same power net +1.2V and the power distribution to CPU1 component as we have done for Power Tree (Figure 5). The same way we will be going over the details in point-by-point approach:

  • First and foremost, when we look at the information for Current Sources, we see a ‘Voltage’ value, which may be confusing. The value reported in this table is 0.7247V (8), which is different from the reported value of 0.977V in Power Tree on Figure 5 (4). The reason for the difference is that reported voltage value were calculated at different locations. As mentioned earlier, the reported voltage in the Power Tree is the voltage at the positive pin of the Current Source. The voltage reported in Element Data is the voltage at the negative pin of the Current Source, which doesn’t include the voltage drop across the ground plane of the return path.

To verify the reported voltage values, we can place Voltage Probes (under circuit elements). Once we do that, we will need to rerun the simulation in order to get the results for the probes:

  1. Two terminals of the ‘VPROBE_1’ attached at the positive pin of Voltage Source and at the positive pin of the Current Source. This probe should show us the voltage difference between VRM and IC, which also the same as reported Voltage Drop ΔV. And as we can see ‘VPROBE_1’ = 222.4637mV (13), when ΔV = 222.464mV (3). Correlated perfectly!
  2. Two terminals of the ‘VPROBE_GND’ attached to the negative pin of the Current Source and negative pin of the Voltage Source. The voltage shown by this probe is the voltage drop across the ground plane.

If we have 1.2V at the positive pin of VRM, then voltage drops 222.464mV across the power plane, so the positive pin of IC gets supplied with 0.977V. Then the voltage at the Current Source 0.724827V (8) being drawn, leaving us with (1.2V – 0.222464V – 0.724827V) = 0.252709V at the negative pin of the Current Source. On the return path the voltage drops again across the ground plane 252.4749mV (14) delivering back at the negative pin of VRM (0.252709V – 0.252475V) = 234uV. This is the internal voltage drop in the Voltage Source, as calculated as output current at VRM 234A (7) multiplied by Parasitic Resistance 1E-6Ohm (Figure 3) at VRM. This is Series R Voltage (11)

  • Parallel R Current of the Current source is calculated as Voltage 724.82mV (8) divided by Parasitic Resistance of the Current Source (Figure 3) 5E+7 Ohm = 1.44965E-8 (9)
  • Current of the Voltage Source report in the Element Data 234A (10) is the same value as reported in the Power Tree (sum of all currents of Current Sources for the +1.2V power net) = 234A (7). Knowing this value of the current we can multiple it by Parasitic Resistance of the Voltage Source (Figure 3) 1E-6 Ohm = (234A * 1E-6Ohm) = 234E-6V, which is equal to reported Series R Voltage (11). And considering that the 234A is the output current of the Voltage Source, we can multiple it by output voltage Vout = 1.2V to get a Power Output = (234A * 1.2V) = 280.85W (12)
Fig. 6. DC IR simulated data viewed in the table format as ‘Element Data’

In addition to all provided above calculations and explanations, the video below in Figure 7 highlights all the key points of this article.

Fig. 7. Difference between reporting Voltage values in Power Tree and Element Data

Conclusion

By carefully reviewing the Power Tree and Element Data reporting options, we can determine many important decisions about the power delivery network quality, such as how much voltage gets delivered to the Current Source; how much voltage drop is on the power net and on the ground net, etc. More valuable information can be extracted from other DC IR results options, such as ‘Loop Resistance’, ‘Path Resistance’, ‘RL table’, ‘Spice Netlist’, full ‘Report’. However, all these features deserve a separate topic.

As always, if you would like to receive more information related to this topic or have any questions please reach out to us at info@padtinc.com.

Reduce EMI with Good Signal Integrity Habits

Recently the ‘Signal Integrity Journal’ posted their ‘Top 10 Articles’ of 2019. All of the articles included were incredible, however, one stood out to me from the rest – ‘Seven Habits of Successful 2-Layer Board Designers’ by Dr. Eric Bogatin (https://www.signalintegrityjournal.com/blogs/12-fundamentals/post/1207-seven-habits-of-successful-2-layer-board-designers). In this work, Dr. Bogatin and his students were developing a 2-Layer printed circuit board (PCB), while trying to minimize signal and power Integrity issues as much as possible. As a result, they developed a board and described seven ‘golden habits’ for this board development. These are fantastic habits that I’m confident we can all agree with. In particular, there was one habit at which I wanted to take a deeper look:

“…Habit 4: When you need to route a cross-under on the bottom layer, make it short. When you can’t make it short, add a return strap over it..”

Generally speaking, this habit suggests to be very careful with the routing of signal traces over the gap on the ground plane. From the signal integrity point of view, Dr. Bogatin explained it perfectly – “..The signal traces routed above this gap will see a gap in the return path and generate cross talk to other signals also crossing the gap..”. On one hand, crosstalk won’t be a problem if there are no other nets around, so the layout might work just fine in that case. However, crosstalk is not the only risk. Fundamentally, crosstalk is an EMI problem. So, I wanted to explore what happens when this habit is ignored and there are no nearby nets to worry about.

To investigate, I created a simple 2-Layer board with the signal trace, connected to 5V voltage source, going over an air gap. Then I observed the near field and far field results using ANSYS SIwave solution. Here is what I found.

Near and Far Field Analysis

Typically, near and far fields are characterized by solved E and H fields around the model. This feature in ANSYS SIwave gives the engineer the ability to simulate both E and H fields for near field analysis, and E field for Far Field analysis.

First and foremost, we can see, as expected, that both near and far Field have resonances at the same frequencies. Additionally, we can observe from Figure 1 that both E and H fields for near field have the largest radiation spikes at 786.3 MHz and 2.349GHz resonant frequencies.

Figure 1. Plotted E and H fields for both Near and Far Field solutions

If we plot E and H fields for Near Field, we can see at which physical locations we have the maximum radiation.

Figure 2. Plotted E and H fields for Near field simulations

As expected, we see the maximum radiation occurring over the air gap, where there is no return path for the current. Since we know that current is directly related to electromagnetic fields, we can also compute AC current to better understand the flow of the current over the air gap.

Compute AC Currents (PSI)

This feature has a very simple setup interface. The user only needs to make sure that the excitation sources are read correctly and that the frequency range is properly indicated. A few minutes after setting up the simulation, we get frequency dependent results for current. We can review the current flow at any simulated frequency point or view the current flow dynamically by animating the plot.

Figure 3. Computed AC currents

As seen in Figure 3, we observe the current being transferred from the energy source, along the transmission line to the open end of the trace. On the ground layer, we see the return current directed back to the source. However at the location of the air gap there is no metal for the return current to flow, therefore, we can see the unwanted concentration of energy along the plane edges. This energy may cause electromagnetic radiation and potential problems with emission.

If we have a very complicated multi-layer board design, it won’t be easy to simulate current flow on near and far fields for the whole board. It is possible, but the engineer will have to have either extra computing time or extra computing power. To address this issue, SIwave has a feature called EMI Scanner, which helps identify problematic areas on the board without running full simulations.

EMI Scanner

ANSYS EMI Scanner, which is based on geometric rule checks, identifies design issues that might result in electromagnetic interference problems during operation. So, I ran the EMI Scanner to quickly identify areas on the board which may create unwanted EMI effects. It is recommended for engineers, after finding all potentially problematic areas on the board using EMI Scanner, to run more detailed analyses on those areas using other SIwave features or HFSS.

Currently the EMI Scanner contains 17 rules, which are categorized as ‘Signal Reference’, ‘Wiring/Crosstalk’, ‘Decoupling’ and ‘Placement’. For this project, I focused on the ‘Signal Reference’ rules group, to find violations for ‘Net Crossing Split’ and ‘Net Near Edge of Reference’. I will discuss other EMI Scanner rules in more detail in a future blog (so be sure to check back for updates).

Figure 4. Selected rules in EMI Scanner (left) and predicted violations in the project (right)

As expected, the EMI Scanner properly identified 3 violations as highlighted in Figure 4. You can either review or export the report, or we can analyze violations with iQ-Harmony. With this feature, besides generating a user-friendly report with graphical explanations, we are also able to run ‘What-if’ scenarios to see possible results of the geometrical optimization.

Figure 5. Generated report in iQ-Harmony with ‘What-If’ scenario

Based on these results of quick EMI Scanner, the engineer would need to either redesign the board right away or to run more analysis using a more accurate approach.

Conclusion

In this blog, we were able to successfully run simulations using ANSYS SIwave solution to understand the effect of not following Dr.Bogatin’s advice on routing the signal trace over the gap on a 2-Layer board. We also were able to use 4 different features in SIwave, each of which delivered the correct, expected results.

Overall, it is not easy to think about all possible SI/PI/EMI issues while developing a complex board. In these modern times, engineers don’t need to manufacture a physical board to evaluate EMI problems. A lot of developmental steps can now be performed during simulations, and ANSYS SIwave tool in conjunction with HFSS Solver can help to deliver the right design on the first try.

If you would like more information or have any questions please reach out to us at info@padtinc.com.

Investigating Signal Integrity: Finding Problems Before They Find You – Webinar

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Introducing Signal Integrity: What is it and how does it impact you? – Webinar

Don’t miss this informative presentation – Secure your spot today!
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If this is your first time registering for one of our Bright Talk webinars, simply click the link and fill out the attached form. We promise that the information you provide will only be shared with those promoting the event (PADT).

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Exploring High-Frequency Electromagnetic Theory with ANSYS HFSS

I recently had the opportunity to present an interesting experimental research paper at DesignCon 2017, titled Replacing High-Speed Bottlenecks with PCB Superhighways. The motivation behind the research was to develop a new high-speed signaling system using rectangular waveguides, but the most exciting aspect for me personally was salvaging a (perhaps contentious) 70 year old first-principles electromagnetic model. While it took some time to really understand how to apply the mathematics to design, their application led to an exciting convergence of theory, simulation, and measurement.

One of the most critical aspects of the design was exciting the waveguide with a monopole probe antenna. Many different techniques have been developed to match the antenna impedance to the waveguide impedance at the desired frequency, as well as increase the bandwidth. Yet, all of them rely on assumptions and empirical measurement studies. Optimizing a design to nanometer precision empirically would be difficult at best and even if the answer was found it wouldn’t inherently reveal the physics. To solve this problem, we needed a first-principles model, a simulation tool that could quickly iterate designs accurately, and some measurements to validate the simulation methodology.

A rigorous first-principles model was developed by Robert Collin in 1960, but this solution has since been forgotten and replaced by simplified rules. Unfortunately, these simplified rules are unable to deliver an optimal design or offer any useful insight to the critical parameters. In fairness, Collin’s equations are difficult to implement in design and validating them with measurement would be tedious and expensive. Because of this, empirical measurements have been considered a faster and cheaper alternative. However, we wanted the best of both worlds… we wanted the best design, for the lowest cost, and we wanted the results quickly.

For this study, we used ANSYS HFSS to simulate our designs. Before exploring new designs, we first wanted to validate our simulation methodology by correlating results with available measurements. We were able to demonstrate a strong agreement between Collin’s theory, ANSYS HFSS simulation, and VNA measurement.

Red simulated S-parameters strongly correlated with blue measurements.

To perform a series of parametric studies, we swept thousands of antenna design iterations across a wide frequency range of 50 GHz for structures ranging from 50-100 guide wavelengths long. High-performance computing gave us the ability to solve return loss and insertion loss S-parameters within just a few minutes for each design iteration by distributing across 48 cores.

Sample Parametric Design Sweep

Finally, we used the lessons we learned from Collin’s equations and the parametric study to develop a new signaling system with probe antenna performance never before demonstrated. You can read the full DesignCon paper here. The outcome also pertains to RF applications in addition to potentially addressing Signal Integrity concerns for future high-speed communication channels.

Rules-of-thumb are important to fast and practical design, but their application can many times be limited. Competitive innovation demands we explore beyond these limitations but the only way to match the speed and accuracy of design rules is to use simulations capable of offering fast design exploration with the same reliability as measurement. ANSYS HFSS gave us the ability to, not only optimize our design, but also teach us about the physics that explain our design and allow us to accurately predict the behavior of new innovative designs.

Investigation Signal Integrity: How to find problems before they find you – Webinar

In the Age of IoT, electronics continue to get smaller, faster, more power efficient, and are integrated into everything around us. Increasingly, companies are incorporating simulation early in the product development process, when the cost of design changes are at their lowest, to meet the challenges presented by Signal Integrity. For this to be effective, simulation tools need to be easy-to-use, compatible with existing work flows, and accurate, all while delivering meaningful results quickly.

If you or your company are designing or using electronics that are:
Critical to revenue, performance, or safety
Getting smaller, faster, or more efficient
Communicating with Gbps data rates
Using several or new connectors
Using long cables or backplanes
Then you could be a victim of Signal Integrity failure!

Join us September 7th, 2016 at 1 pm Pacific Time for this free webinar to discover how ANSYS is delivering intuitive Signal Integrity analysis solutions that can easily import ECAD geometry to compute SYZ parameters, inter-trace coupling, or impedance variations. Learn how ANSYS can help identify Signal Integrity problems and optimize potential solutions faster and cheaper than prototyping multiple iterations.

This webinar will introduce:

  • What products ANSYS provides for Signal Integrity problems
  • How these products can integrate into existing design workflows
  • And how easy these products are to use, even for novice operators

Followed by a Q&A session!

Click Here to register for this event and be sure to add it to your calendar to receive reminders.

Can’t make it? We suggest you register regardless, as our webinars are recorded and sent out along with a PDF of the presentation to our contacts within 24 hours of the presentation finishing.

Introducing Signal Integrity: What is it and how does it impact you? – Webinar

Is your comapny designing or using electronics that are:
  • Critical to revenue, performance, or safety
  • Designed in-house or by 3rd parties
  • Using wireless technology (e.g. Wi-Fi, Bluetooth)
  • Connecting to the cloud or Internet of Things (IoT)
  • Collecting large sets of data
  • Getting smaller, faster, or more efficient
If so then you could potentially be a victim of signal integrity failure!
Join us August 17th, 2016 at 1 pm Pacific Time for a free webinar covering an introduction to Signal Integrity

This is a high-level introduction that will cover:
  • What Signal Integrity is
  • Some of the challenges related to it
  • How to identify those at risk of signal integrity related failure
  • What is being done in response
Followed by a Q&A session afterwards!

Click Here to register for this event and be sure to add it to your calendar to receive reminders.

 

Can’t make it? We suggest you register regardless, as our webinars are recorded and sent out along with a PDF of the presentation to our contacts within 24 hours of the presentation finishing.

An Eye for the Win! – Signal Integrity with ANSYS

DDRComparisonIn today’s world of high speed communication we are continuously pushing the envelope in data throughput and reliability – There are many challenges that restrict speedy progress: Time – Spinning multiple boards to find and fix problems costs valuable time and money; Cost – additional test procedures can significantly add to this cost; Scalability of Solutions – it’s fundamentally difficult to accurately predict what might happen solely through previous experiences; which is often why multiple spins are required.

ANSYS has the simulation platform that enable signal integrity engineers to predict and improve the performance of high speed communication channels before any board is prototyped – Imagine being able get the design right the first time by testing several design parameters such as different trace routing, power profiles and components.

This sounds like a great proposition but in actuality what do you get from doing that? The answer is a reduced design cost, detailed insight into the design and a reduced time to market. The only way to obtain this “full picture” is to understand the electrical, thermal and mechanical aspects of the design.

EyediagramEye Diagram of Data Signal Obtained in ANSYS

A critical characterization in high speed communication channel design is the Eye diagram. Extensive testing is done to obtain Eye diagrams for various signal nets across a PCB or Package – ANSYS can provide the Eye diagram so that engineers can address potential failures and weaknesses in their design before it is sent out for prototyping. Bathtub curves, effects of jitter and identifying crosstalk are equally important in the design of communication channels and all can be obtained and considered with ANSYS tools.

ANSYS supports IBIS-AMI modeling, SERDES design, TDR measurement and Statistical Eye analysis among much more. With chip, memory and board manufacturers all utilizing ANSYS products it is easy to incorporate and analyze real world product performance of the entire PCB.

TDRTDR Measurement Across Net

ANSYS allows all aspects of the design to be tested and optimized before prototyping. Apart from signal integrity ANSYS tools can also accurately model power integrity concerns such as decoupling capacitor optimization, thermal response and structural issues, as well as cooling solutions for chips, packages, PCBs and full electronic systems. With the ability to analyze and help optimize different design characteristics of a PCB, ANSYS can provide engineers with “the full picture” to help reduce cost and time to market, and to understand the design’s expected real world operation.

VoltageDropBoardWarpageElectronicsCooling

Top: Voltage Drop; Middle: PCB Warpage;
Bottom: Cooling Flow Through Enclosure

The “Eye” is only a phone call away.

Please give us a call at 1-800-293-PADT or reach out to me directly at manoj@padtinc.com for more information.

Getting to know ANSYS – SIwave

This video is an introduction to ANSYS SIwave – an analysis tool for Integrated Circuits and PCBs