Welcome to a New Era in Electronics Reliability Simulation

Simulation itself is no longer a new concept in engineering, but individual fields, applications, and physics are continually improved upon and integrated into the toolbox that is an engineer’s arsenal. Many times, these are incremental additions to a particular solver’s capabilities or a more specialized method of post processing, however this can also occasionally be present through new cross-connections between separate tools or even an entirely new piece of software. As a result of all this, Ansys has now reached critical mass for its solution space surrounding Electronics Reliability. That is, we can essentially approach an electronics reliability problem from any major physics perspective that we like.

So, what is Electronics Reliability and what physics am I referring to? Great question, and I’m glad you asked – I’d like to run through some examples of each physics and their typical use-case / importance, as well as where Ansys fits in. Of course, real life is a convoluted Multiphysics problem in most cases, so having the capability to accommodate and link many different physics together is also an important piece of this puzzle.

Running down the list, we should perhaps start with the most obvious category given the name – Electrical Reliability. In a broad sense, this encompasses all things related to electromagnetic fields as they pertain to transmission of both power and signals. While the electrical side of this topic is not typically in my wheelhouse, it is relatively straightforward to understand the basics around a couple key concepts, Power Integrity and Signal Integrity.

Power integrity, as its name suggests, is the idea that we need to maintain certain standards of quality for the electrical power in a device/board/system. While some kinds of electronics are robust enough that they will continue to function even under large variations in supplied voltage or current, there are also many that rely on extremely regular power supplies that only vary above certain limits or within narrow bounds. Even if we’re looking at a single PCB (as in the image below), in today’s technological environment it will no doubt have electrical traces mapped all throughout it as well as multiple devices present that operate under their own specified electrical conditions.

Figure 1: An example PCB with complex trace and via layouts, courtesy of Ansys

If we were determined to do so, we could certainly measure trace lengths, widths, thicknesses, etc., and make some educated guesses for the resulting voltage drops to individual components. However, considerably more effort would need to be made to account for bends, corners, or variable widths, and that would still completely neglect any environmental effects or potential interactions between traces. It is much better to be able to represent and solve for the entire geometry at once using a dedicated field solver – this is where Ansys SIwave or Ansys HFSS typically come in, giving us the flexibility to accurately determine the electrical reliability, whether we’re talking about AC or DC power sources.

Signal integrity is very much related, except that “signals” in this context often involve different pathways, less energy, and a different set of regulations and tolerances. Common applications involve Chip-signal modeling and DDRx virtual compliance – these have to do with not only the previous general concerns regarding stability and reliability, but also adherence to specific standards (JEDEC) through virtual compliance tests. After all, inductive electromagnetic effects can still occur over nonconductive gaps, and this can be a significant source of noise and instability in cases where conductive paths (like board traces or external connections) cross or run very near each other.

Figure 2: Example use-cases in virtual compliance testing, courtesy of Ansys

Whether we are looking at timings between components, transition times, jitter, or even just noise, HFSS and SIWave can both play roles here. In either case, being able to use a simulation environment to confirm that a certain design will or will not meet certain standards can provide invaluable feedback to the design process.

Other relevant topics to Electrical Reliability may include Electromagnetic Interference (EMI) analysis, antenna performance, and Electrostatic Discharge (ESD) analysis. While I will not expand on these in great detail here, I think it is enough to realize that an excellent electrical design (such as for an antenna) requires some awareness of the operational environment. For instance, we might want to ensure that our chosen or designed component will adequately function while in the presence of some radiation environment, or maybe we would like to test the effectiveness of the environmental shielding on a region of our board. Maybe, there is some concern about the propagation of an ESD through a PCB, and we would like to see how vulnerable certain components are. Ansys tools provide us the capabilities needed to do all of this.

The second area of primary interest is Thermal Reliability, as just about anyone who has worked with or even used electronics knows, they generate some amount of heat while in use. Of course, the quantity, density, and distribution of that heat can vary tremendously depending on the exact device or system under question, but this heat will ultimately result in a rise in temperature somewhere. The point of thermal reliability basically boils down to realizing that the performance and function of many electrical components depends on their temperature. Whether it is simply a matter of accounting for a change in electrical conductivity as temperature rises or a hard limit of functionality for a particular transistor at 150 °C, acknowledging and accounting for these thermal effects is critical when considering electronics reliability. This is a problem with several potential solutions depending on the scale of interest, but generally we cover the package/chip, board, and full system levels. For the component/chip level, a designer will often want to provide some package level specs for OEMs so that a component can be properly scoped in a larger design. Ansys Icepak has toolkits available to help with this process; whether it is simplifying a 3D package down to a detailed network thermal model or identifying the most critical hot spot within a package based on a particular heat distribution. Typically, network models are generated through temperature measurements taken from a sample in a standardized JEDEC test chamber, but Icepak can assist through automatically generating these test environments, as below, and then using simulation results to extract well defined JB and JC values for the package under test.

Figure 3: Automatically generated JEDEC test chambers created by Ansys Icepak, courtesy of Ansys

On the PCB level of detail, we are likely interested in how heat moves across the entire board from component to component or out to the environment. Ansys Icepak lets us read in a detailed ECAD description for said PCB and process its trace and via definitions into an accurate thermal conductivity map that will improve our simulation accuracy. After all, two boards with identical sizing and different copper trace layouts may conduct heat very differently from each other.

Figure 4: Converting ECAD information into thermal conductivity maps using Ansys Icepak, courtesy of Ansys

On the system level of thermal reliability, we are likely looking at the effectiveness of a particular cooling solution on our electronic design. Icepak makes it easy to include the effects of a heat exchanger (like a coldplate) without having to explicitly model its computationally expensive geometry by using a flow network model. Also, many of today’s electronics are expected to constantly run right up against their limit and are kept within thermal spec by using software to throttle their input power in conjunction with an existing cooling strategy. We can use Icepak to implement and test these dynamic thermal management algorithms so that we can track and evaluate their performance across a range of environmental conditions.

The next topic that we should consider is that of Mechanical Reliability. Mechanical concepts tend to be a little more intuitive and relatable due to their more hands-on nature than the other two, though the exact details behind the cause and significance of stresses in materials is of course more involved. In the most general sense, stress is a result of applying force to an object. If this stress is high compared to what is allowed by a material, then bad things tend to happen – like permanent deformation or fracture. For electronic devices consisting of many materials, small structures, and particularly delicate components, we have once again surpassed what can be reasonably accomplished with hand calculations. Whether we are looking at an individual package, the integrity of an entire PCB, or the stability that a rigid housing will provide to a set of PCBs, Ansys has a solution. We might use Ansys Mechanical to look at manufacturing allowances for the permissible force used while mounting a complicated leaded component onto a board, as seen below. Or maybe, we will use mechanical simulation to find the optimal positioning of leads on a new package such that its natural vibrational frequencies are outside normal ambient conditions.

Figure 5: A surface component with discretely modeled leads, courtesy of Ansys

At the PCB level, we face many of the same detail-oriented challenges around representing traces and vias that have been mentioned for the electrical applications. They may not be quite as critical and more easily approximated in some ways, but that does not change the fact that copper traces are mechanically quite different from the resin composites often used as the substrate (like FR-4). Ansys tools like Sherlock provide best in class PCB modeling on this front, allowing us to directly bring in ECAD models with full trace and component detail, and then model them mechanically at several different levels depending on the exact need. Automating a materials property averaging scheme based on the local density of traces may be sufficient if we are looking at the general bending behavior of a board, but we can take it to the next level by explicitly modeling traces as “reinforcement” elements. This brings us to the level of detail where we can much more reliably look at the stresses present in individual traces, such that we can make good design decisions to reduce the risk of traces peeling or delaminating from the surface.

Figure 6: Example trace mapping workflow and methods, courtesy of Ansys

Beyond just looking at possible improvements in the design process, we can also make use of Ansys tools like LS-DYNA or Mechanical to replicate testing or accident conditions that an existing design could be subjected to. As a real-world example, many of us are all too familiar with the occasional consequences of accidentally dropping our smart phones – Ansys is used to test designs against these kind of shock events, where impact against a hard surface can result in high stresses in key locations. This helps us understand where to reinforce a design to protect against the worst damage or even what angle of impact is most likely to cause an operational failure.

As the finale for all of this, I come back to the first comment of reality being a complex Multiphysics problem. Many of the previous topics are not truly isolated to their respective physics (as much as we often simplify them as such), and this is one of the big ways in which the Ansys ecosystem shines: Comprehensive Multiphysics. For the topic of thermal reliability, I simply stated that electronics give off heat. This may be obvious, but that heat is not just a magical result of the device being turned on but is instead a physical and calculable result of the actual electrical behavior. Indeed, this the exact kind of result that we can extract from one of the relevant electronics tools. An HFSS solution will provide us with not only the electrical performance of an antenna but also the three-dimensional distribution of heat that is consequently produced. Ansys lets us very easily feed this information into an Icepak simulation, which then has the ability to give us far more accurate results than a typical uniform heat load assumption provides.

Figure 7: Coupled electrical-thermal simulation between HFSS and Icepak, courtesy of Ansys

If we find that our temperatures are particularly high, we might then decide to bring these results back into HFSS to locally change material properties as a function of temperature to get an even more accurate set of electrical results. It could be that this results in an appreciable shift in our antenna’s frequency, or perhaps the efficiency has decreased, and aspects of the design need to be revisited. These are some of the things that we would likely miss without a comprehensive Multiphysics environment.

On a more mechanical side, the effects on stress and strain from thermal conditions are very well known and understood at this point, but there is no reason we could not use Ansys to bring the electrical alongside this established thermal-mechanical behavior. After all, what is a better representation of the real physics involved than using SIwave or HFSS to model the electrical behavior of a PCB, bringing those result into an Icepak simulation as a heat load to test the performance of a cooling loop or heat sink, and then using at least some of those thermal results to look at stresses through not only a PCB as a whole but also individual traces? Not a whole lot at this moment in time, I would say.

The extension that we can make on these examples, is that they have by and large been representative cases of how an electronics device responds to a particular event or condition and judging its reliability metrics based on that set of results, however many physics might be involved. There is one more piece of the puzzle we have access to that also interweaves itself throughout the Multiphysics domain and that is Reliability Physics. This is mostly relevant to us in electronics reliability for considering how different events, or even just a repetition of the same event, can stack together and accumulate to contribute towards some failure in the future. An easy example of this is a plastic hinge or clip that you might find on any number of inexpensive products – flexing a thin piece of plastic like in these hinges can provide a very convenient method of motion for quite some time, but that hinge will gradually accumulate damage until it inevitably cracks and fails. Every connection within a PCB is susceptible to this same kind of behavior, whether it is the laminations of the PCB itself, the components soldered to the surface, or even the individual leads on a component. If our PCB is mounted on the control board of a bus, satellite, or boat, there will be some vibrations and thermal cycles associated with its life. A single one of these events may be of much smaller magnitude and seemingly negligible compared to something dramatic like a drop test, and yet they can still add up to the point of being significant over a period of months or years.

This is exactly the kind of thing that Ansys Sherlock proves invaluable for: letting us define and track the effect of events that may occur over a PCB’s entire lifecycle. Many of these will revolve around mechanical concepts of fatigue accumulating as a result of material stresses, but it is still important to consider the potential Multiphysics origins of stress. Different simulations will be required for each of mechanical bending during assembly, vibration during transport, and thermal cycling during operation, yet each of these contributes towards the final objective of electronics reliability. Sherlock will bring each of these and more together in a clear description of which components on a board are most likely to fail, how likely they are to fail as a function of time, and which life events are the most impactful.

Figure 8: Example failure predictions over the life cycle of a PCB using Ansys Sherlock, courtesy of Ansys

Really, what all of this comes down to is that when we design and create products, we generally want to make sure that they function in the way that we intend them to. This might be due to a personal pride in our profession or even just the desire to maximize profit through minimizing the costs associated with a component failure, however at the end it just makes sense to anticipate and try to prevent the failures that might occur under normal operating conditions.

For complex problems like electronics devices, there are many physics all intimately tied together in the consideration of overall reliability, but the Ansys ecosystem of tools allows us to approach these problems in a realistic way. Whether we’re looking at the electrical reliability of a circuit or antenna, the thermal performance of a cooling solution or algorithm, or the mechanical resilience of a PCB mounted on a bracket, Ansys provides a path forward.

If you have any questions or would like to learn more, please contact us at info@padtinc.com or visit www.padtinc.com.

Setting up and Solving a PCB and Enclosure for Thermal Simulation in Ansys Icepak Electronic Desktop

The thought of setting up and running a complex PCB and Enclosure thermal model was something that used to strike fear in the heart of engineers. That is no longer true. In this video, we step through the process of importing, setting up, and solving a PCB thermal simulation.

If you have any questions or would like to learn more, please contact us at info@padtinc.com or www.padtinc.com.

High Frequency Updates in Ansys 2021 R1 – Webinar

Whether leveraging improved workflows or leading-edge capabilities with Ansys 2021 R1, teams are tackling design challenges head on, eliminating the need to make costly workflow tradeoffs, developing next-generation innovations with increased speed and significantly enhancing productivity, all in order to deliver high-quality products to market faster than ever.

When it comes to high frequency electromagnetics, Ansys 2021 R1 delivers a plethora of groundbreaking enhancements. Ansys HFSS Mesh Fusion enables simulation of large, never before possible electromagnetic systems with efficiency and scalability. This release also allows for encrypted 3D components supported in HFSS 3D Layout for PCBs, IC packages and IC designs to enable suppliers to share detailed 3D component designs for creating highly accurate simulations.

Join PADT’s Lead Electromagnetics Engineer and high frequency expert Michael Griesi for a presentation on updates made to the Ansys HF suite in the 2021 R1 release, including advancements for:

  • Electronics Desktop
  • HFSS
  • Circuits
  • EMIT
  • And Much More

Register Here

If this is your first time registering for one of our Bright Talk webinars, simply click the link and fill out the attached form. We promise that the information you provide will only be shared with those promoting the event (PADT).

You will only have to do this once! For all future webinars, you can simply click the link, add the reminder to your calendar and you’re good to go!

Making Sense of DC IR Results in Ansys SIwave

In this article I will cover a Voltage Drop (DC IR) simulation in SIwave, applying realistic power delivery setup on a simple 4-layer PCB design. The main goal for this project is to understand what data we receive by running DC IR simulation, how to verify it, and what is the best way of using it.

And before I open my tools and start diving deep into this topic, I would like to thank Zachary Donathan for asking the right questions and having deep meaningful technical discussions with me on some related subjects. He may not have known, but he was helping me to shape up this article in my head!

Design Setup

There are many different power nets present on the board under test, however I will be focusing on two widely spread nets +1.2V and +3.3V. Both nets are being supplied through Voltage Regulator Module (VRM), which will be assigned as a Voltage Source in our analysis. After careful assessment of the board design, I identified the most critical components for the power delivery to include in the analysis as Current Sources (also known as ‘sinks’). Two DRAM small outline integrated circuit (SOIC) components D1 and D2 are supplied with +1.2V. While power net +3.3V provides voltage to two quad flat package (QFP) microcontrollers U20 and U21, mini PCIE connector, and hex Schmitt-Trigger inverter U1.

Fig. 1. Power Delivery Network setting for a DC IR analysis

Figure 1 shows the ‘floor plan’ of the DC IR analysis setup with 1.2V voltage path highlighted in yellow and 3.3V path highlighted in light blue.

Before we assign any Voltage and Current sources, we need to define pin groups for all nets +1.2V, +3.3V and GND for all PDN component mentioned above. Having pin groups will significantly simplify the reviewing process of the results. Also, it is generally a good practice to start the DC IR analysis from the ‘big picture’ to understand if certain component gets enough power from the VRM. If a given IC reports an acceptable level of voltage being delivered with a good margin, then we don’t need to dig deeper; we can instead focus on those which may not have good enough margins.

Once we have created all necessary pin groups, we can assign voltage and current sources. There are several ways of doing that (using wizard or manual), for this project we will use ‘Generate Circuit Element on Components’ feature to manually define all sources. Knowing all the components and having pin groups already created makes the assignment very straight-forward. All current sources draw different amount of current, as indicated in our setting, however all current sources have the same Parasitic Resistance (very large value) and all voltage source also have the same Parasitic Resistance (very small value). This is shown on Figure 2 and Figure 3.

Note: The type of the current source ‘Constant Voltage’ or ‘Distributed Current’ matters only if you are assigning a current source to a component with multiple pins on the same net, and since in this project we are working with pins groups, this setting doesn’t make difference in final results.

Fig. 2. Voltage and Current sources assigned
Fig. 3. Parasitic Resistance assignments for all voltage and current sources

For each power net we have created a voltage source on VRM and multiple current sources on ICs and the connector. All sources have a negative node on a GND net, so we have a good common return path. And in addition, we have assigned a negative node of both voltage sources (one for +1.2V and one for +3.3V) as our reference points for our analysis. So reported voltage values will be referenced to that that node as absolute 0V.

At this point, the DC IR setup is complete and ready for simulation.

Results overview and validation

When the DC IR simulation is finished, there is large amount of data being generated, therefore there are different ways of viewing results, all options are presented on Figure 4. In this article I will be primarily focusing on ‘Power Tree’ and ‘Element Data’. As an additional source if validation we may review the currents and voltages overlaying the design to help us to visualize the current flow and power distribution. Most of the time this helps to understand if our assumption of pin grouping is accurate.

Fig. 4. Options to view different aspects of DC IR simulated data

Power Tree

First let’s look at the Power Tree, presented on Figure 5. Two different power nets were simulated, +1.2V and +3.3V, each of which has specified Current Sources where the power gets delivered. Therefore, when we analyze DC IR results in the Power tree format, we see two ‘trees’, one for each power net. Since we don’t have any pins, which would get both 1.2V and 3.3V at the same time (not very physical example), we don’t have ‘common branches’ on these two ‘trees’.

Now, let’s dissect all the information present in this power tree (taking in consideration only one ‘branch’ for simplicity, although the logic is applicable for all ‘branches’):

  • We were treating both power nets +1.2V and +3.3V as separate voltage loops, so we have assigned negative nodes of each Voltage Source as a reference point. Therefore, we see the ‘GND’ symbol ((1) and (2)) for each voltage source. Now all voltage calculations will be referenced to that node as 0V for its specific tree.
  • Then we see the path from Voltage Source to Current Source, the value ΔV shows the Voltage Drop in that path (3). Ultimately, this is the main value power engineers usually are interested in during this type of analysis. If we subtract ΔV from Vout we will get the ‘Actual Voltage’ delivered to the specific current source positive pin (1.2V – 0.22246V = 0.977V). That value reported in the box for the Current Source (4). Technically, the same voltage drop value is reported in the column ‘IR Drop’, but in this column we get more details – we see what the percentage of the Vout is being dropped. Engineers usually specify the margin value of the acceptable voltage drop as a percentage of Vout, and in our experiment we have specified 15%, as reported in column ‘Specification’. And we see that 18.5% is greater than 15%, therefore we get ‘Fail_I_&_V’ results (6) for that Current Source.
  • Regarding the current – we have manually specified the current value for each Current Source. Current values in Figure 2 are the same as in Figure 5. Also, we can specify the margin for the current to report pass or fail. In our example we assigned 108A as a current at the Current Source (5), while 100A is our current limit (4). Therefore, we also got failed results for the current as well.
  • As mentioned earlier, we assigned current values for each Current Source, but we didn’t set any current values for the Voltage Source. This is because the tool calculates how much current needs to be assigned for the Voltage Source, based on the value at the Current Sources. In our case we have 3 Current Sources 108A, 63A, 63A (5). The sum of these three values is 234A, which is reported as a current at the Voltage Source (7). Later we will see that this value is being used to calculate output power at the Voltage Source.  
Fig. 5. DC IR simulated data viewed as a ‘Power Tree’

Element Data

This option shows us results in the tabular representation. It lists many important calculated data points for specific objects, such as bondwire, current sources, all vias associated with the power distribution network, voltage probes, voltage sources.

Let’s continue reviewing the same power net +1.2V and the power distribution to CPU1 component as we have done for Power Tree (Figure 5). The same way we will be going over the details in point-by-point approach:

  • First and foremost, when we look at the information for Current Sources, we see a ‘Voltage’ value, which may be confusing. The value reported in this table is 0.7247V (8), which is different from the reported value of 0.977V in Power Tree on Figure 5 (4). The reason for the difference is that reported voltage value were calculated at different locations. As mentioned earlier, the reported voltage in the Power Tree is the voltage at the positive pin of the Current Source. The voltage reported in Element Data is the voltage at the negative pin of the Current Source, which doesn’t include the voltage drop across the ground plane of the return path.

To verify the reported voltage values, we can place Voltage Probes (under circuit elements). Once we do that, we will need to rerun the simulation in order to get the results for the probes:

  1. Two terminals of the ‘VPROBE_1’ attached at the positive pin of Voltage Source and at the positive pin of the Current Source. This probe should show us the voltage difference between VRM and IC, which also the same as reported Voltage Drop ΔV. And as we can see ‘VPROBE_1’ = 222.4637mV (13), when ΔV = 222.464mV (3). Correlated perfectly!
  2. Two terminals of the ‘VPROBE_GND’ attached to the negative pin of the Current Source and negative pin of the Voltage Source. The voltage shown by this probe is the voltage drop across the ground plane.

If we have 1.2V at the positive pin of VRM, then voltage drops 222.464mV across the power plane, so the positive pin of IC gets supplied with 0.977V. Then the voltage at the Current Source 0.724827V (8) being drawn, leaving us with (1.2V – 0.222464V – 0.724827V) = 0.252709V at the negative pin of the Current Source. On the return path the voltage drops again across the ground plane 252.4749mV (14) delivering back at the negative pin of VRM (0.252709V – 0.252475V) = 234uV. This is the internal voltage drop in the Voltage Source, as calculated as output current at VRM 234A (7) multiplied by Parasitic Resistance 1E-6Ohm (Figure 3) at VRM. This is Series R Voltage (11)

  • Parallel R Current of the Current source is calculated as Voltage 724.82mV (8) divided by Parasitic Resistance of the Current Source (Figure 3) 5E+7 Ohm = 1.44965E-8 (9)
  • Current of the Voltage Source report in the Element Data 234A (10) is the same value as reported in the Power Tree (sum of all currents of Current Sources for the +1.2V power net) = 234A (7). Knowing this value of the current we can multiple it by Parasitic Resistance of the Voltage Source (Figure 3) 1E-6 Ohm = (234A * 1E-6Ohm) = 234E-6V, which is equal to reported Series R Voltage (11). And considering that the 234A is the output current of the Voltage Source, we can multiple it by output voltage Vout = 1.2V to get a Power Output = (234A * 1.2V) = 280.85W (12)
Fig. 6. DC IR simulated data viewed in the table format as ‘Element Data’

In addition to all provided above calculations and explanations, the video below in Figure 7 highlights all the key points of this article.

Fig. 7. Difference between reporting Voltage values in Power Tree and Element Data

Conclusion

By carefully reviewing the Power Tree and Element Data reporting options, we can determine many important decisions about the power delivery network quality, such as how much voltage gets delivered to the Current Source; how much voltage drop is on the power net and on the ground net, etc. More valuable information can be extracted from other DC IR results options, such as ‘Loop Resistance’, ‘Path Resistance’, ‘RL table’, ‘Spice Netlist’, full ‘Report’. However, all these features deserve a separate topic.

As always, if you would like to receive more information related to this topic or have any questions please reach out to us at info@padtinc.com.

Reduce EMI with Good Signal Integrity Habits

Recently the ‘Signal Integrity Journal’ posted their ‘Top 10 Articles’ of 2019. All of the articles included were incredible, however, one stood out to me from the rest – ‘Seven Habits of Successful 2-Layer Board Designers’ by Dr. Eric Bogatin (https://www.signalintegrityjournal.com/blogs/12-fundamentals/post/1207-seven-habits-of-successful-2-layer-board-designers). In this work, Dr. Bogatin and his students were developing a 2-Layer printed circuit board (PCB), while trying to minimize signal and power Integrity issues as much as possible. As a result, they developed a board and described seven ‘golden habits’ for this board development. These are fantastic habits that I’m confident we can all agree with. In particular, there was one habit at which I wanted to take a deeper look:

“…Habit 4: When you need to route a cross-under on the bottom layer, make it short. When you can’t make it short, add a return strap over it..”

Generally speaking, this habit suggests to be very careful with the routing of signal traces over the gap on the ground plane. From the signal integrity point of view, Dr. Bogatin explained it perfectly – “..The signal traces routed above this gap will see a gap in the return path and generate cross talk to other signals also crossing the gap..”. On one hand, crosstalk won’t be a problem if there are no other nets around, so the layout might work just fine in that case. However, crosstalk is not the only risk. Fundamentally, crosstalk is an EMI problem. So, I wanted to explore what happens when this habit is ignored and there are no nearby nets to worry about.

To investigate, I created a simple 2-Layer board with the signal trace, connected to 5V voltage source, going over an air gap. Then I observed the near field and far field results using ANSYS SIwave solution. Here is what I found.

Near and Far Field Analysis

Typically, near and far fields are characterized by solved E and H fields around the model. This feature in ANSYS SIwave gives the engineer the ability to simulate both E and H fields for near field analysis, and E field for Far Field analysis.

First and foremost, we can see, as expected, that both near and far Field have resonances at the same frequencies. Additionally, we can observe from Figure 1 that both E and H fields for near field have the largest radiation spikes at 786.3 MHz and 2.349GHz resonant frequencies.

Figure 1. Plotted E and H fields for both Near and Far Field solutions

If we plot E and H fields for Near Field, we can see at which physical locations we have the maximum radiation.

Figure 2. Plotted E and H fields for Near field simulations

As expected, we see the maximum radiation occurring over the air gap, where there is no return path for the current. Since we know that current is directly related to electromagnetic fields, we can also compute AC current to better understand the flow of the current over the air gap.

Compute AC Currents (PSI)

This feature has a very simple setup interface. The user only needs to make sure that the excitation sources are read correctly and that the frequency range is properly indicated. A few minutes after setting up the simulation, we get frequency dependent results for current. We can review the current flow at any simulated frequency point or view the current flow dynamically by animating the plot.

Figure 3. Computed AC currents

As seen in Figure 3, we observe the current being transferred from the energy source, along the transmission line to the open end of the trace. On the ground layer, we see the return current directed back to the source. However at the location of the air gap there is no metal for the return current to flow, therefore, we can see the unwanted concentration of energy along the plane edges. This energy may cause electromagnetic radiation and potential problems with emission.

If we have a very complicated multi-layer board design, it won’t be easy to simulate current flow on near and far fields for the whole board. It is possible, but the engineer will have to have either extra computing time or extra computing power. To address this issue, SIwave has a feature called EMI Scanner, which helps identify problematic areas on the board without running full simulations.

EMI Scanner

ANSYS EMI Scanner, which is based on geometric rule checks, identifies design issues that might result in electromagnetic interference problems during operation. So, I ran the EMI Scanner to quickly identify areas on the board which may create unwanted EMI effects. It is recommended for engineers, after finding all potentially problematic areas on the board using EMI Scanner, to run more detailed analyses on those areas using other SIwave features or HFSS.

Currently the EMI Scanner contains 17 rules, which are categorized as ‘Signal Reference’, ‘Wiring/Crosstalk’, ‘Decoupling’ and ‘Placement’. For this project, I focused on the ‘Signal Reference’ rules group, to find violations for ‘Net Crossing Split’ and ‘Net Near Edge of Reference’. I will discuss other EMI Scanner rules in more detail in a future blog (so be sure to check back for updates).

Figure 4. Selected rules in EMI Scanner (left) and predicted violations in the project (right)

As expected, the EMI Scanner properly identified 3 violations as highlighted in Figure 4. You can either review or export the report, or we can analyze violations with iQ-Harmony. With this feature, besides generating a user-friendly report with graphical explanations, we are also able to run ‘What-if’ scenarios to see possible results of the geometrical optimization.

Figure 5. Generated report in iQ-Harmony with ‘What-If’ scenario

Based on these results of quick EMI Scanner, the engineer would need to either redesign the board right away or to run more analysis using a more accurate approach.

Conclusion

In this blog, we were able to successfully run simulations using ANSYS SIwave solution to understand the effect of not following Dr.Bogatin’s advice on routing the signal trace over the gap on a 2-Layer board. We also were able to use 4 different features in SIwave, each of which delivered the correct, expected results.

Overall, it is not easy to think about all possible SI/PI/EMI issues while developing a complex board. In these modern times, engineers don’t need to manufacture a physical board to evaluate EMI problems. A lot of developmental steps can now be performed during simulations, and ANSYS SIwave tool in conjunction with HFSS Solver can help to deliver the right design on the first try.

If you would like more information or have any questions please reach out to us at info@padtinc.com.